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order this document by MC68HC11Kts/d ?motorola inc., 1997 this document contains information on a new product. speci?ations and information herein are subject to change without notice. motorola semiconductor technical data m68hc11 k series technical summary 8-bit microcontroller the m68hc11 k-series microcontroller units (mcus) are high-performance derivatives of the mc68hc11f1 and have several additional features. the MC68HC11K0, MC68HC11K1, MC68HC11K3, MC68HC11K4 and mc68hc711k4 comprise the series. these mcus, with a nonmul- tiplexed expanded bus, are characterized by high speed and low power consumption. their fully static design allows operation at frequencies from 4 mhz to dc. this document contains information concerning standard, custom-rom, and extended-voltage devic- es. standard devices include those with disabled rom (MC68HC11K1), disabled eeprom (MC68HC11K3), disabled rom and eeprom (MC68HC11K0), or eprom replacing rom (mc68hc711k4). custom-rom devices have a rom array that is programmed at the factory to cus- tomer specifications. extended-voltage devices are guaranteed to operate over a much greater voltage range (3.0 vdc to 5.5 vdc) at lower frequencies than the standard devices. refer to the device ordering information tables for details concerning these differences. 1 features ?m68hc11 cpu ?power saving stop and wait modes ?768 bytes ram (all saved during standby) ?24 kbytes rom or eprom ?640 bytes electrically erasable programmable read only memory (eeprom) ?optional security feature protects memory contents ?on-chip memory mapping logic allows expansion to over 1 mbyte of address space ?prog mode allows use of standard eprom programmer (27c256 footprint) ?nonmultiplexed address and data buses ?four programmable chip selects with clock stretching (expanded modes) ?enhanced 16-bit timer with four-stage programmable prescaler ?three input capture (ic) channels ?four output compare (oc) channels ?one additional channel, selectable as fourth ic or fifth oc ?8-bit pulse accumulator ?four 8-bit or two 16-bit pulse width modulation (pwm) timer channels ?real-time interrupt circuit ?computer operating properly (cop) watchdog ?clock monitor ?enhanced asynchronous nonreturn to zero (nrz) serial communications interface (sci) ?enhanced synchronous serial peripheral interface (spi) ?eight-channel 8-bit analog-to-digital (a/d) converter ?seven bidirectional input/output (i/o) ports (54 pins) ?one fixed input-only port (8 pins) ?available in 84-pin plastic leaded chip carrier (plcc), 84-pin windowed ceramic leaded chip carrier (clcc), and 80-pin quad flat pack (qfp)
motorola m68hc11 k series 2 MC68HC11Kts/d table 1 standard device ordering information package temperature config description frequency mc order number 84-pin plcc ?0 to + 85 c $df buffalo rom 4 mhz MC68HC11K4bcfn4 ?0 to + 85 c $dd no rom 2 mhz MC68HC11K1cfn2 3 mhz MC68HC11K1cfn3 4 mhz MC68HC11K1cfn4 ?0 to + 105 c $dd no rom 2 mhz MC68HC11K1vfn2 3 mhz MC68HC11K1vfn3 4 mhz MC68HC11K1vfn4 ?0 to + 125 c $dd no rom 2 mhz MC68HC11K1mfn2 3 mhz MC68HC11K1mfn3 4 mhz MC68HC11K1mfn4 ?0 to + 85 c $dc no rom, no eeprom 2 mhz MC68HC11K0cfn2 3 mhz MC68HC11K0cfn3 4 mhz MC68HC11K0cfn4 ?0 to + 105 c $dc no rom, no eeprom 2 mhz MC68HC11K0vfn2 3 mhz MC68HC11K0vfn3 4 mhz MC68HC11K0vfn4 ?0 to + 125 c $dc no rom, no eeprom 2 mhz MC68HC11K0mfn2 3 mhz MC68HC11K0mfn3 4 mhz MC68HC11K0mfn4 ?0 to + 85 c $df otprom 2 mhz mc68hc711k4cfn2 3 mhz mc68hc711k4cfn3 4 mhz mc68hc711k4cfn4 ?0 to + 105 c $df otprom 2 mhz mc68hc711k4vfn2 3 mhz mc68hc711k4vfn3 4 mhz mc68hc711k4vfn4 ?0 to + 125 c $df otprom 2 mhz mc68hc711k4mfn2 3 mhz mc68hc711k4mfn3 4 mhz mc68hc711k4mfn4 80-pin qfp (14 mm x 14 mm) ?0 to + 85 c $df buffalo rom 4 mhz MC68HC11K4bcfu4 ?0 to + 85 c $dd no rom 2 mhz MC68HC11K1cfu2 3 mhz MC68HC11K1cfu3 4 mhz MC68HC11K1cfu4 ?0 to + 105 c $dd no rom 2 mhz MC68HC11K1vfu2 3 mhz MC68HC11K1vfu3 4 mhz MC68HC11K1vfu4 ?0 to + 85 c $dc no rom, no eeprom 2 mhz MC68HC11K0cfu2 3 mhz MC68HC11K0cfu3 4 mhz MC68HC11K0cfu4 ?0 to + 105 c $dc no rom, no eeprom 2 mhz MC68HC11K0vfu2 3 mhz MC68HC11K0vfu3 4 mhz MC68HC11K0vfu4
m68hc11 k series motorola MC68HC11Kts/d 3 84-pin clcc (windowed) ?0 to + 85 c $df eprom 2 mhz mc68hc711k4cfs2 3 mhz mc68hc711k4cfs3 4 mhz mc68hc711k4cfs4 ?0 to + 105 c $df eprom 2 mhz mc68hc711k4vfs2 3 mhz mc68hc711k4vfs3 4 mhz mc68hc711k4vfs4 ?0 to + 125 c $df eprom 2 mhz mc68hc711k4mfs2 3 mhz mc68hc711k4mfs3 4 mhz mc68hc711k4mfs4 table 2 extended voltage (3.0 vdc to 5.5 vdc) device ordering information package temperature description frequency mc order number 84-pin plcc ?0 to + 70 c custom rom 1 mhz mc68l11k4fn1 3 mhz mc68l11k4fn3 no rom 1 mhz mc68l11k1fn1 3 mhz mc68l11k1fn3 no rom, no eeprom 1 mhz mc68l11k0fn1 3 mhz mc68l11k0fn3 custom rom, no eeprom 1 mhz mc68l11k3fn1 3 mhz mc68l11k3fn3 80-pin qfp ?0 to + 70 c custom rom 1 mhz mc68l11k4fu1 3 mhz mc68l11k4fu3 no rom 1 mhz mc68l11k1fu1 3 mhz mc68l11k1fu3 no rom, no eeprom 1 mhz mc68l11k0fu1 3 mhz mc68l11k0fu3 custom rom, no eeprom 1 mhz mc68l11k3fu1 3 mhz mc68l11k3fu3 table 1 standard device ordering information (continued) package temperature config description frequency mc order number
motorola m68hc11 k series 4 MC68HC11Kts/d table 3 custom rom device ordering information package temperature description frequency mc order number 84-pin plcc ?0 to + 85 c custom rom 2 mhz MC68HC11K4cfn2 3 mhz MC68HC11K4cfn3 4 mhz MC68HC11K4cfn4 ?0 to + 105 c custom rom 2 mhz MC68HC11K4vfn2 3 mhz MC68HC11K4vfn3 4 mhz MC68HC11K4vfn4 ?0 to + 125 c custom rom 2 mhz MC68HC11K4mfn2 3 mhz MC68HC11K4mfn3 4 mhz MC68HC11K4mfn4 ?0 to + 85 c custom rom, no eeprom 2 mhz MC68HC11K3cfn2 3 mhz MC68HC11K3cfn3 4 mhz MC68HC11K3cfn4 ?0 to + 105 c custom rom, no eeprom 2 mhz MC68HC11K3vfn2 3 mhz MC68HC11K3vfn3 4 mhz MC68HC11K3vfn4 ?0 to + 125 c custom rom, no eeprom 2 mhz MC68HC11K3mfn2 3 mhz MC68HC11K3mfn3 4 mhz MC68HC11K3mfn4 80-pin qfp ?0 to + 85 c custom rom 2 mhz MC68HC11K4cfu2 3 mhz MC68HC11K4cfu3 4 mhz MC68HC11K4cfu4 ?0 to + 105 c custom rom 2 mhz MC68HC11K4vfu2 3 mhz MC68HC11K4vfu3 4 mhz MC68HC11K4vfu4 ?0 to + 85 c custom rom, no eeprom 2 mhz MC68HC11K3cfu2 3 mhz MC68HC11K3cfu3 4 mhz MC68HC11K3cfu4 ?0 to + 105 c custom rom, no eeprom 2 mhz MC68HC11K3vfu2 3 mhz MC68HC11K3vfu3 4 mhz MC68HC11K3vfu4
m68hc11 k series motorola MC68HC11Kts/d 5 figure 1 pin assignments for 84-pin plcc/clcc pb6/addr14 pa0/ic3 pb7/addr15 pb1/addr9 pb4/addr12 pb3/addr11 v ss pb5/addr13 pb2/addr10 pa2/ic1 pa3/oc5/ic4/oc1 pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 v dd pa1/ic2 25 26 12 13 14 15 16 17 18 19 20 59 73 72 71 70 69 68 67 66 65 64 21 22 23 24 63 62 61 60 27 74 pg7/r/w pg6 ph7/csprog ph6/csgp2 ph5/csgp1 ph4/csio ph3/pw4 ph2/pw3 ph1/pw2 ph0/pw1 xirq /v ppe 2 test16 1 test15 1 v dd v ss test14 1 pc6/data6 v dd v ss pc7/data7 pc5/data5 pc4/data4 pd2/miso pd1/txd pd0/rxd moda/lir modb/v stby reset xtal extal xout e 8 7 6 5 4 2 83 82 81 80 10 9 84 11 40 41 42 43 44 45 33 34 35 36 37 38 39 46 47 48 pg0/xa13 pe5/an5 av dd pe4/an4 pe6/an6 pe7/an7 pe3/an3 v rh v rl pe0/an0 pe1/an1 pe2/an2 av ss pf7/addr7 pf6/addr6 pf5/addr5 MC68HC11K series 79 58 pc3/data3 pg5/xa18 28 pf4/addr4 49 1 pb0/addr8 78 77 76 75 pa7/pai/oc1 pd5/ss pd4/sck pd3/mosi 3 pf3/addr3 pf2/addr2 pf1/addr1 pf0/addr0 50 51 52 53 pc2/data2 pc1/data1 pc0/data0 irq 57 56 55 54 pg4/xa17 pg3/xa16 pg2/xa15 pg1/xa14 29 30 31 32 1. pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry. 2. v ppe applies only to devices with eprom.
motorola m68hc11 k series 6 MC68HC11Kts/d figure 2 pin assignments for 80-pin 14 mm x 14 mm tqfp xtal e extal pd1/txd modb/v stby moda/lir v dd reset pd0/rxd pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 v ss pc7/data7 14 15 1 2 3 4 5 6 7 8 9 45 59 58 57 56 55 54 53 52 51 50 10 11 12 13 49 48 47 46 16 60 pb6/addr14 pb5/addr13 pa3/oc5/ic4/oc1 pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 pd5/ss pd4/sck pd3/mosi pa1/ic2 pa2/ic1 pa0/ic3 v dd v ss pb7/addr15 pe2/an2 v rl pe0/an0 pe1/an1 pe3/an3 pe4/an4 pf0/addr0 pf1/addr1 pf2/addr2 pf3/addr3 pf4/addr4 pf5/addr5 pf6/addr6 pf7/addr7 av ss v rh 77 76 75 74 73 70 71 68 67 66 65 79 78 69 80 28 29 30 31 32 33 21 22 23 24 25 26 27 34 35 36 pb0/addr8 ph3/pw4 ph0/pw1 ph4/csio ph2/pw3 ph1/pw2 ph5/csgp1 v ss v dd xirq ph7/csprog ph6/csgp2 pg7/r/w pg6 pg5/xa18 pg4/xa17 MC68HC11K series 64 44 pe5/an5 pb4/addr12 17 pg3/xa16 37 pd2/miso 72 63 62 61 pc1/data1 pc0/data0 irq pg0/xa13 pg2/xa15 pg1/xa14 38 39 40 pb3/addr11 pb2/addr10 pb1/addr9 18 19 20 pe6/an6 pe7/an7 av dd 43 42 41
m68hc11 k series motorola MC68HC11Kts/d 7 figure 3 m68hc11 k-series block diagram cop periodic spi sci chip selects an0 port e an1 an2 an3 an4 an5 an6 an7 a/d converter mode control timer system cpu v rl v rh pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 port h ddr port h ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph7 pd0 pd1 pd2 pd3 pd4 pd5 csio csgp1 csgp2 csprog port d ddr port d miso mosi sck ss rxd txd modb/ moda/ 640 bytes eeprom 768 bytes ram interrupt pulse accumulator address bus data bus pa0 port a ddr pa1 pa2 pa3 pa4 pa5 pa6 pa7 ic3 ic2 ic1 oc5/ic4/oc1 oc4/oc1 oc3/oc1 oc2/oc1 pai/oc1 oscillator interrupt logic clock logic pc0 port c ddr pc1 pc2 pc3 pc4 pc5 pc6 pc7 data0 data1 data2 data3 data4 data5 data6 data7 port c pf0 port f pf1 pf2 pf3 pf4 pf5 pf6 pf7 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 pb0 port b pb1 pb2 pb3 pb4 pb5 pb6 pb7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 port a r/w xirq /v ppe irq reset xtal extal e * xout lir v stby memory expansion port g ddr port g pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 xa15 xa16 xa17 xa18 pwm pw4 pw3 pw2 pw1 xa14 xa13 v dd v ss av dd av ss (k1, k4) 0 kbytes eeprom (k0, k3) 24 kbytes rom/ (k3, k4) eprom 0 kbytes rom/ (k0, k1) eprom port b ddr port f ddr * xout pin omitted on 80-pin qfp.
section page motorola m68hc11 k series 8 MC68HC11Kts/d 1 features 1 2 operating modes 11 2.1 single-chip operating mode ..................................................................................................... 11 2.2 expanded operating mode ....................................................................................................... 11 2.3 bootstrap mode ......................................................................................................................... 11 2.4 special test mode ..................................................................................................................... 11 2.5 mode selection .......................................................................................................................... 11 3 on-chip memory 14 3.1 memory map and register block .............................................................................................. 14 3.2 ram .......................................................................................................................................... 17 3.3 rom/eprom ............................................................................................................................ 18 3.4 eeprom ................................................................................................................................... 22 3.5 configuration control register (config) ................................................................................. 24 3.6 security feature ........................................................................................................................ 25 4 memory expansion and chip selects 27 4.1 memory expansion .................................................................................................................... 27 4.2 overlap guidelines .................................................................................................................... 30 4.3 chip selects .............................................................................................................................. 30 4.3.1 program chip select (csprog) ................................................................................... 31 4.3.2 i/o chip select (csio) ................................................................................................... 31 4.3.3 general-purpose chip selects (csgp1, csgp2) ......................................................... 32 4.3.4 chip select priorities ...................................................................................................... 32 4.3.5 chip select control registers ........................................................................................ 32 4.3.6 examples of memory expansion using chip selects ..................................................... 35 5 resets and interrupts 38 6 parallel input/output 42 7 serial communications interface 49 8 serial peripheral interface 56 9 analog-to-digital converter 60 10 main timer 64 10.1 real-time interrupt ................................................................................................................... 70 11 pulse accumulator 71 12 pulse-width modulation timer 74 12.1 pwm boundary cases .............................................................................................................. 78 table of contents
m68hc11 k series motorola MC68HC11Kts/d 9 c cforc timer compare force $000b 66 config system configuration register $003f 25 coprst arm/reset cop timer circuitry $003a 40 cscstr chip select clock stretch $005a 33 csctl chip select control $005b 32 d ddra data direction register for port a $0001 42 ddrb data direction register for port b $0002 43 ddrf data direction register for port f $0003 46 ddrg data direction register for port g $007f 47 ddrh data direction register for port h $007d 46 e eprog eprom programming control $002b 19 g gpcs1a general-purpose chip select 1 address $005c 33 gpcs1c general-purpose chip select 1 control $005d 34 gpcs2a general-purpose chip select 2 address $005e 34 gpcs2c general-purpose chip select 2 control $005f 34 h hprio highest priority i-bit interrupt and miscellaneous $003c 11, 40 i init ram and register mapping $003d 18 init2 eeprom mapping $0037 24 m mmsiz memory mapping size $0056 28 mmwbr memory mapping window base $0057 29 o oc1d output compare 1 data $000d 66 oc1m output compare 1 mask $000c 66 opt2 system configuration options 2 $0038 12, 44, 59 option system configuration options $0039 39 p pacnt pulse accumulator counter $0027 73 pactl pulse accumulator control $0026 73 pgar port g assignment $002d 28, 47 porta port a data $0000 42 portb port b data $0004 43 portc port c data $0006 43 porte port e data $000a 46 portf port f data $0005 46 portg port g data $007e 47 porth port h data $007c 46 ppar port pull-up assignment $002c 48 pprog eeprom programming control $003b 22 pwclk pulse-width modulation clock select $0060 62, 76 register index
motorola m68hc11 k series 10 MC68HC11Kts/d pwcnt[4:1] pulse-width modulation timer counter 1 to 4 $0064?0067 77 pwdty[4:1] pulse-width modulation timer duty cycle 1 to 4 $006c?006f 78 pwen pulse-width modulation timer enable $0063 77 pwper[4:1] pulse-width modulation timer period 1 to 4 $0068?006b 78 pwpol pulse-width modulation timer polarity $0061 62, 76 pwscal pulse-width modulation timer prescaler $0062 63, 77 s scbdh/l sci baud rate control high/low $0070, $0071 52 sccr1 sci control 1 $0072 45, 52 sccr2 sci control 2 $0073 53 scsr1 sci status register 1 $0074 54 scsr2 sci status register 2 $0075 55 spcr serial peripheral control $0028 45 spcr serial peripheral control register $0028 57 spdr spi data $002a 58 spsr serial peripheral status register $0029 58 t tcnt timer count $000e, $000f 66 tctl2 timer control 2 $0021 67 tflg2 timer interrupt flag 2 $0025 69, 72 ti4/o5 timer input capture 4/output compare 5 $001e?001f 67 tmsk1 timer interrupt mask 1 $0022 68 tmsk2 timer interrupt mask 2 $0024 68, 72 toc1?oc4 timer output compare $0016?001d 67
m68hc11 k series motorola MC68HC11Kts/d 11 2 operating modes the m68hc11 k-series mcus have four modes of operation that directly affect the address space. these modes are described as follows. 2.1 single-chip operating mode in single-chip operating mode, the m68hc11 k-series mcus are stand-alone microcontrollers with no external address or data bus. addressing range is 64 kbytes and is limited to on-chip resources. refer to the memory map diagram. 2.2 expanded operating mode in expanded operating mode, the mcu has a 64 kbyte address range and, using the expansion bus, can access external resources within the 64 kbyte space. this space includes the same on-chip mem- ory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral and memory devices. addressing beyond 64 kbytes is available only in expanded mode using the on- chip, register-based memory mapping logic. the additional address lines for memory expansion (xa[18:13]) are implemented as alternate functions of port g. the expansion bus (external address and data buses) is made up of ports b, c, and f, and the r/w signal. in expanded operating mode, high order address bits are output on the port b pins, low order address bits on the port f pins, and the data bus on port c. refer to the memory map diagram. 2.3 bootstrap mode bootstrap mode allows special-purpose programs to be loaded into internal ram. the mcu contains 448 bytes of bootstrap rom which is enabled and present in the memory map only when the device is in bootstrap mode. the bootstrap rom contains a program which initializes the sci and allows the user to download up to 768 bytes of code into on-chip ram. after a four-character delay, or after receiving the character for address $037f, control passes to the loaded program at $0080. refer to the memory map diagram. refer also to application note m68hc11 bootstrap mode (an1060/d). 2.4 special test mode special test mode is used primarily for factory testing. in this operating mode, rom/eprom is removed from the address space and interrupt vectors are accessed externally at $bfc0?bfff. 2.5 mode selection operating modes are selected by a combination of logic levels applied to two input pins (moda and modb) during reset. the logic level present (at the rising edge of reset) on these inputs is reflected in bits in the hprio register. after reset, the operating mode may be changed according to the table con- tained in the description of the hprio register. the functions of two features that are enabled by bits in opt2 register are dependent upon the operat- ing mode. lir driven is enabled with the lirdv bit. internal read visibility/not e is enabled with the irvne bit. refer to the opt2 register description that follows hprio. *the reset values of rboot, smod, and mda depend on the mode selected at power up. hprio ?ighest priority i-bit interrupt and miscellaneous $003c bit 7 654321 bit 0 rboot* smod* mda* psel4 psel3 psel2 psel1 psel0 reset: 0 0 0 0 0 1 1 0 single chip 00100110 expanded 11000110 bootstrap 01100110 special test
motorola m68hc11 k series 12 MC68HC11Kts/d rboot ?read bootstrap rom/eprom valid only when smod is set (bootstrap or special test mode). can only be written in special modes. 0 = bootstrap rom disabled and not in map 1 = bootstrap rom enabled and in map at $be00?bfff smod and mda ?pecial mode select and mode select a these two bits can be read at any time. they can be written anytime in special modes. mda can only be written once in normal modes. smod cannot be set once it has been cleared. psel[4:0] ?riority select bits [4:0] refer to 5 resets and interrupts . *can be written only once in normal modes. can be written anytime in special modes. lirdv ?ir driven in single-chip and bootstrap modes, this bit has no meaning or effect. the lir pin is normally configured for wired-or operation (only pulls low). in order to detect consecutive instructions in a high-speed ap- plication, this signal can be made to drive high for a short time to prevent false triggering. 0 = lir not driven high out of reset 1 = lir driven high for one quarter cycle to reduce transition time cwom ?ort c wired-or mode refer to 6 parallel input/output . bit 5 ?ot implemented always read zero irvne ?nternal read visibility/not e irvne can be written only once in normal modes (smod = 0). in special modes irvne can be written any time. in special test mode, irvne is reset to one. in all other modes, irvne is reset to zero. in expanded modes this bit determines whether irv is on or off. 0 = no internal read visibility on external bus 1 = data from internal reads is driven out the external data bus. in single-chip modes this bit determines whether the e clock drives out from the chip. 0 = e is driven out from the chip. 1 = e pin is driven low. refer to the following table. inputs latched at reset modb moda mode smod mda 1 0 single chip 0 0 1 1 expanded 0 1 0 0 bootstrap 1 0 0 1 special test 1 1 opt2 system configuration options 2 $0038 bit 7 654321 bit 0 lirdv cwom irvne* lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0 mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne can be written single chip 0 on off e once expanded 0 on off irv once boot 0 on off e anytime special test 1 on on irv anytime
m68hc11 k series motorola MC68HC11Kts/d 13 lsbf ?sb first enable refer to 8 serial peripheral interface . spr2 ?pi clock rate select refer to 8 serial peripheral interface . xdv[1:0] ?out clock divide select controls the frequency of the clock driven out of the xout pin xdv [1:0] xout = extal divided by frequency at extal = 8 mhz frequency at extal = 12 mhz frequency at extal = 16 mhz 0 0 1 8 mhz 12 mhz 16 mhz 0 1 4 2 mhz 3 mhz 4 mhz 1 0 6 1.3 mhz 2 mhz 2.7 mhz 1 1 8 1 mhz 1.5 mhz 2 mhz
motorola m68hc11 k series 14 mc6hc11kts/d 3 on-chip memory in general, k-series mcus have 768 bytes ram, 640 bytes eeprom, and 24 kbytes rom/eprom. some devices in the series have portions of their memory resources disabled. some have rom and some have eprom replacing rom. the following paragraphs describe the memory systems of devices in the series. 3.1 memory map and register block the init, init2, and config registers control the presence and location of the registers, ram, ee- prom, and rom/eprom in the 64 kbyte cpu address space. the 128-byte register block originates at $0000 after reset and can be placed at any 4 kbyte boundary ($x000) after reset by writing an ap- propriate value to the init register. refer to figure 4 . figure 4 memory map expanded 24 kbytes rom/eprom (can be remapped to $2000?7fff or $a000?ffff by the config register) ffc0 ffff normal mode interrupt vectors 128-byte register block (can be remapped to any 4k page by the init register) 768 bytes ram (can be remapped to any 4k page by the init register) single chip bootstrap special test ext ext ext $0000 $1000 $a000 $ffff x000 x07f xd80 xfff a000 ffff bfc0 bfff special mode interrupt vectors ext boot rom (only present in bootstrap mode) be00 x080 x37f 640 bytes eeprom (can be remapped to any 4k page by the init2 register) reserved (special test mode only) xd7f xd00 note: rom/eprom can be enabled in special test mode by setting romon bit in the config register after reset.
m68hc11 k series motorola mc6hc11kts/d 15 figure 5 ram and register mapping table 4 m68hc11 k series register and control bit assignments (can be remapped to any 4-kbyte boundary) bit 7 654321 bit 0 $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $0001 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra $0002 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb $0003 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf $0004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $0005 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf $0006 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $0007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $0008 0 0 pd5 pd4 pd3 pd2 pd1 pd0 portd $0009 0 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd $000a pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $000b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $000c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $000d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $000e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $000f bit 7 654321 bit 0 tcnt (low) $0010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $0011 bit 7 654321 bit 0 tic1 (low) $0012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $0013 bit 7 654321 bit 0 tic2 (low) $0014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $0000 $007f $0080 $02ff $0300 $037f $407f $4000 $12ff $1080 $107f $1000 $0000 $007f $0000 $007f $0080 $02ff init = $00 reg @ $0000 ram @ $0080 init = $10 reg @ $0000 ram @ $1000 init = $04 reg @ $4000 ram @ $0000 register block register block ram a ram a ram b ram b ram a ram b register block
motorola m68hc11 k series 16 mc6hc11kts/d $0015 bit 7 654321 bit 0 tic3 (low) $0016 bit 15 14 13 12 11 10 9 bit 8 toc1(high) $0017 bit 7 654321 bit 0 toc1 (low) $0018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $0019 bit 7 654321 bit 0 toc2 (low) $001a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $001b bit 7 654321 bit 0 toc3 (low) $001c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $001d bit 7 654321 bit 0 toc4 (low) $001e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (high) $001f bit 7 654321 bit 0 ti4/o5 (low) $0020 om2 ol2 om3 ol3 om4 ol4 om5 ol5 tctl1 $0021 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a tctl2 $0022 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tmsk1 $0023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $0024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $0025 tof rtif paovf paif 0000 tflg2 $0026 0 paen pamod pedge 0 i4/o5 rtr1 rtr0 pactl $0027 bit 7 654321 bit 0 pacnt $0028 spie spe dwom mstr cpol cpha spr1 spr0 spcr $0029 spif wcol 0 modf 0 0 0 bit 0 spsr $002a bit 7 654321 bit 0 spdr $002b mbe 0 elat excol exrow t1 t0 epgm eprog* $002c 0000 hppue gppue fppue bppue ppar $002d 0 0 pgar5 pgar4 pgar3 pgar2 pgar1 pgar0 pgar $002e reserved $002f reserved $0030 ccf 0 scan mult cd cc cb ca adctl $0031 bit 7 654321 bit 0 adr1 $0032 bit 7 654321 bit 0 adr2 $0033 bit 7 654321 bit 0 adr3 $0034 bit 7 654321 bit 0 adr4 $0035 bulkp lvpen bprt4 ptcon bprt3 bprt2 bprt1 bprt0 bprot $0036 reserved $0037 ee3 ee2 ee1 ee0 0000 init2 $0038 lirdv cwom 0 irvne lsbf spr2 xdv1 xdv0 opt2 $0039 adpu csel irqe dly cme fcme cr1 cr0 option $003a bit 7 654321 bit 0 coprst $003b odd even lvpi byte row erase eelat eepgm pprog $003c rboot smod mda psel4 psel3 psel2 psel1 psel0 hprio $003d ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 init $003e tilop 0 occr cbyp disr fcm fcop 0 test1 $003f romad 1 clkx paren nosec nocop romon eeon config $0040 reserved to $0055 reserved $0056 mxgs2 mxgs1 w2sz1 w2sz0 0 0 w1sz1 w1sz0 mmsiz $0057 w2a15 w2a14 w2a13 0 w1a15 w1a14 w1a13 0 mmwbr table 4 m68hc11 k series register and control bit assignments (continued) (can be remapped to any 4-kbyte boundary) bit 7 654321 bit 0
m68hc11 k series motorola mc6hc11kts/d 17 *mc68hc711k4 only. 3.2 ram all members of the m68hc11 k series have 768 bytes of static ram. the ram can be mapped to any 4-kbyte boundary. upon reset, the ram is mapped at $0080?037f. the registers are also mapped to this 4-kbyte boundary. in previous versions of the m68hc11 devices the register block being mapped to the same boundary would cause the portion of ram overlapped by the register block to be lost. how- ever, a new ram remapping feature has been added which automatically allows all of the ram to be accessible even if the register block overlaps the ram. because the registers are located in the same $0058 0 x1a18 x1a17 x1a16 x1a15 x1a14 x1a13 0 mm1cr $0059 0 x2a18 x2a17 x2a16 x2a15 x2a14 x2a13 0 mm2cr $005a iosa iosb gp1sa gp1sb gp2sa gp2sb pcsa pcsb cscstr $005b ioen iopl iocsa iosz gcspr pcsen pcsza pcszb csctl $005c g1a18 g1a17 g1a16 g1a15 g1a14 g1a13 g1a12 g1a11 gpcs1a $005d g1dg2 g1dpc g1pol g1av g1sza g1szb g1szc g1szd gpcs1c $005e g2a18 g2a17 g2a16 g2a15 g2a14 g2a13 g2a12 g2a11 gpcs2a $005f 0 g2dpc g2pol g2av g2sza g2szb g2szc g2szd gpcs2c $0060 con34 con12 pcka2 pcka1 0 pckb3 pckb2 pckb1 pwclk $0061 pclk4 pclk3 pclk2 pclk1 ppol4 ppol3 ppol2 ppol1 pwpol $0062 bit 7 654321 bit 0 pwscal $0063 tpwsl discp 0 0 pwen4 pwen3 pwen2 pwen1 pwen $0064 bit 7 654321 bit 0 pwcnt1 $0065 bit 7 654321 bit 0 pwcnt2 $0066 bit 7 654321 bit 0 pwcnt3 $0067 bit 7 654321 bit 0 pwcnt4 $0068 bit 7 654321 bit 0 pwper1 $0069 bit 7 654321 bit 0 pwper2 $006a bit 7 654321 bit 0 pwper3 $006b bit 7 654321 bit 0 pwper4 $006c bit 7 654321 bit 0 pwdty1 $006d bit 7 654321 bit 0 pwdty2 $006e bit 7 654321 bit 0 pwdty3 $006f bit 7 654321 bit 0 pwdty4 $0070 btst bspl 0 sbr12 sbr11 sbr10 sbr9 sbr8 scbdh $0071 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 scbdl $0072 loops woms 0 m wake ilt pe pt sccr1 $0073 tie tcie rie ilie te re rwu sbk sccr2 $0074 tdre tc rdrf idle or nf fe pf scsr1 $0075 0000000raf scsr2 $0076 r8 t8 000000 scdrh $0077 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdrl $0078 reserved to $007b reserved $007c ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 porth $007d ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 ddrh $007e pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg $007f ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg table 4 m68hc11 k series register and control bit assignments (continued) (can be remapped to any 4-kbyte boundary) bit 7 654321 bit 0
motorola m68hc11 k series 18 mc6hc11kts/d 4-kbyte boundary after reset, 128 bytes of the ram are located at $0300 to $037f. remapping is ac- complished by writing appropriate values to the init register. refer to the register and ram mapping examples following the memory map diagram. when power is removed from the mcu, ram contents may be preserved using the modb/v stby pin. a power source (2.0 vdc ? dd ) applied to this pin protects all 768 bytes of ram. can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode. ram[3:0] ?nternal ram map position these bits determine the upper four bits of the ram address. at reset ram is mapped to $0000. nor- mally the ram would be mapped at $0000?02ff (768 bytes). however, the register block overlaps the first 128 bytes of ram, causing them to be remapped to $0300?037f. refer to figure 4 and fig- ure 5 . reg[3:0] ?28-byte register block map position these bits determine the upper four bits of the register block starting address. at reset registers are mapped to $0000 and overlap the first 128 bytes of ram, causing them to be remapped to $0300 $037f. refer to figure 4 and figure 5 . 3.3 rom/eprom standard devices have 24 kbytes of eprom (otprom in a non-windowed package). custom rom devices have a 24-kbyte rom array that is mask programmed at the factory to customer specifications. the MC68HC11K0, MC68HC11K1, mc68l11k0, and mc68l11k1 have no rom/eprom. refer to the ordering information tables . the romad and romon control bits in the config register control the position and presence of rom/eprom in the memory map. the rom/eprom can be mapped at $2000?7fff or $a000 $ffff. if it is mapped to $a000?ffff, vector space is included. in single-chip mode the rom/ eprom is forced to $a000?ffff (romad = 1) and enabled (romon = 1), regardless of the value in the config register. this ensures that there will be rom/eprom at the vector space. in special test mode, the romon bit is forced to zero so that the rom/eprom is removed from the memory map. refer to figure 4 . programming eprom requires an external 12.25 volt nominal power supply (v ppe ) that must be ap- plied to the xirq /v ppe pin. three methods are used to program and verify eprom/otprom. normal eprom/otprom programming can be accomplished in any operating mode. normal pro- gramming is accomplished using the eprom/otprom programming register (eprog). the eprog register enables the eprom programming voltage, controls the latching of data to be programmed, and selects single- or multiple-byte programming. to program the eprom, complete the following steps using the eprog register: 1. set the elat bit in eprog register. eelat bit in pprog must be cleared as it negates the function of the elat bit. 2. write data to the desired address. 3. turn on programming voltage to the eprom array by setting the epgm bit in eprog register. 4. delay for 2 ms or more, as appropriate. 5. clear the epgm bit in eprog to turn off the programming voltage. init ram and register mapping $003d bit 7 654321 bit 0 ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 reset: 0000000 0
m68hc11 k series motorola mc6hc11kts/d 19 6. clear the eprog register to reconfigure the eprom address and data buses for normal op- eration. in eprom emulation mode (prog mode), the eprom/otprom is programmed as a stand-alone eprom by adapting the mcu footprint to the 27c256-type eprom and using an appropriate eprom programmer. to put the mcu in prog mode, pull the following pins low: moda/lir , modb/v stby , reset , pa[2:0]. refer to figure 6 . in the third method, the eprom is programmed by software while in the special test or bootstrap modes. user-developed software can be uploaded through the sci, or a rom resident eprom pro- gramming utility can be used. to use the resident utility, bootload a three-byte program consisting of a single jump instruction to $bf00. $bf00 is the starting address of a resident eprom programming util- ity. the utility program sets the x and y index registers to default values, then receives programming data from an external host and programs it into eprom. the value in ix determines programming delay time. the value in iy is a pointer to the first address in eprom to be programmed (default = $a000). when the utility program is ready to receive programming data, it sends the host the $ff character. then it waits. when the host sees the $ff character, the eprom programming data is sent, starting with the first location in the eprom array. after the last byte to be programmed is sent and the corre- sponding verification data is returned, the programming operation is terminated by resetting the mcu. although the external 12.25 v programming voltage must be applied to the xirq /v ppe pin during eprom programming, it should be equal to v dd before verifying the data that was just programmed. it should equal v dd during normal operation also. the xirq /v ppe pin has a high voltage detect circuit that inhibits assertion of the elat bit when programming voltage is at low levels. caution if the mcu is used in any operating mode while high voltage (12.25 v nominal) is present on the xirq /v ppe pin, the irq /ce pin must be pulled high to avoid acci- dental programming or corruption of eprom contents. after programming an eprom location, irq pin must also be pulled high before the address and data are changed to program the next location. mbe ?ultiple-byte programming enable 0 = eprom array configured for normal programming 1 = program two bytes with the same data when multiple-byte programming is enabled, address bit 5 is considered a don't care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get programmed. mbe can be read in any mode and always reads zero in normal modes. mbe can only be written in special modes. bit 6 ?ot implemented always reads zero elat ?prom latch control elat can be read any time. elat can be written any time except when epgm = 1, then the write to elat will be disabled. when elat = 1, writes to eprom cause address and data to be latched and the eprom cannot be read. 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming eprog eprom programming control $002b bit 7 654321 bit 0 mbe elat excol exrow epgm reset: 0000000 0
motorola m68hc11 k series 20 mc6hc11kts/d excol ?elect extra columns 0 = user array selected 1 = user array is disabled and extra columns are accessed at bits [7:0]. addresses use bits [11:5] and bits [4:0] are don't care. excol can only be read in special modes and always returns zero in normal modes. excol can be written in special modes only. exrow ?elect extra rows 0 = user array selected 1 = user array is disabled and two extra rows are available. addresses use bits [5:0] and bits [11:6] are don't care. exrow can only be read in special modes and always returns zero in normal modes. exrow can be written in special modes only. bits [2:1] ?ot implemented always read zero epgm ?prom programming voltage enable epgm can be read any time and can only be written when elat = 1. 0 = programming voltage to eprom array disconnected 1 = programming voltage to eprom array connected
m68hc11 k series motorola mc6hc11kts/d 21 figure 6 pin assignments of the mc68hc711k4 mcu in prog mode notes: pf4/addr4 pf5/addr5 pf6/addr6 pf1/addr1 pf2/addr2 pf3/addr3 pf7/addr7 pf0/addr0 addr4 addr5 addr6 addr1 addr2 addr3 addr7 addr12 addr8 addr9 addr10 addr11 addr0 pb6/addr14 pb4/addr12 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pc7/data7 pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 pc1/data1 pc0/data0 o7 o6 o5 o1 o2 o4 o3 o0 addr4 addr5 addr6 addr1 addr2 addr3 addr7 addr12 addr8 addr9 addr10 addr11 addr0 addr14 o7 o6 o5 o1 o2 o4 o3 o0 internal 24 kbyte eprom eprom pin functions mcu pin functions eprom mode pin connections mc68hc711k4 irq xirq /v ppe pb7/addr15 ce oe pb5/addr13 addr13 addr13 gnd gnd pa0/ic3 pa3/ic4/oc5/oc1 v ss ce oe v cc v pp pe0/an0 addr14 gnd pa1/ic2 gnd pa2/ic1 gnd pa4/oc4/oc1 gnd pa5/oc3/oc1 gnd pa6/oc2/oc1 gnd pa7/pai/oc1 gnd pg0/xa13 gnd pg1/xa14 gnd pg2/xa15 gnd pg3/xa16 gnd pg4/xa17 gnd pg5/xa18 gnd pg6 gnd pg7/r/w gnd pd0/rxd gnd pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss unused gnd gnd gnd gnd v rl v rh extal xtal e moda/lir modb/v stby reset gnd gnd gnd unused gnd ph0/pw1 ph1/pw2 ph2/pw3 ph3/pw4 ph4/csio ph5/csgp1 ph6/csgp2 ph7/csprog testxx (3) xout pe1/an1 pe2/an2 pe3/an3 pe4/an4 pe5/an5 pe6/an6 pe7/an7 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v ss v ss v dd v cc v pp outputs inputs note 3 note 4 note 1 note 2 note 1 note 4 1. unused inputs ?grounding is recommended. 2. unused inputs ?these pins may be left unterminated. 3. unused outputs ?these pins should be left unconnected. 4. grounding these six pins configures the mc68hc711k4 for eprom emulation mode.
motorola m68hc11 k series 22 mc6hc11kts/d 3.4 eeprom the 640-byte eeprom is initially located at $0d80 after reset, assuming eeprom is enabled in the memory map by the eeon bit in the config register. eeprom can be placed at any 4-kbyte bound- ary ($xd80) by writing appropriate values to the init2 register. note that eeprom can be mapped so that it contains the vector space. refer to figure 4 . the MC68HC11K0, MC68HC11K3, mc68l11k0, and mc68l11k3 have no eeprom. refer to the ordering information tables . programming and erasing the eeprom is controlled by the pprog register, and dependent upon the block protect (bprot) register value. an on-chip charge pump develops the high voltage required for programming and erasing. when the frequency of the e clock is less than 1 mhz, select the internal clock source to drive the eeprom charge pump by writing one to the csel bit in the option register. the config register consists of a single eeprom byte. although the byte is not included in the 640- byte eeprom array, programming the config register requires the same procedure as any byte in the array. the erased state of bits in the config register is logic one. refer to the config register description that follows this section. the erased state of an eeprom byte is $ff (all ones). to erase the eeprom, ensure that the proper bits of the bprot register are cleared, then complete the following steps using the pprog register: 1. set the erase, eelat, and appropriate byte and row bits in pprog register. 2. write to the appropriate eeprom address with any data. row erase only requires a write to any location in the row. bulk erase is done by writing to any location in the array. 3. set the erase, eelat, eepgm, and appropriate byte and row bits in pprog register. 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the programming voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. to program the eeprom, ensure the proper bits of the bprot register are cleared and use the pprog register to complete the following steps: 1. set the eelat bit in pprog register. 2. write data to the desired address. 3. set eepgm bit in pprog. 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the programming voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. caution since it is possible to perform other operations while the eeprom programming/ erase operation is in progress, it is common to start the operation and then return to the main program until the 10 ms is completed. when the eelat bit is set at the beginning of a program/erase operation, the eeprom is electronically removed from the memory map; thus, it is not accessible during the program/erase cycle. care must be taken to ensure that eeprom resources will not be needed by any routines in the code during the 10 ms program/erase time. pprog ?eprom programming control $003b bit 7 654321 bit 0 odd even lvpi byte row erase eelat eepgm reset: 0000000 0
m68hc11 k series motorola mc6hc11kts/d 23 odd ?rogram odd rows in half of eeprom (test) even ?rogram even rows in half of eeprom (test) lvpi ?ow voltage programming inhibit lvpi can be read at any time and writes to lvpi have no meaning nor effect. lvpi is set if lvpen bit in bprot register equals one and the lvpi circuit detects that v dd has fallen below a safe operating voltage. once set, lvpi is cleared when v dd returns to a safe operating voltage or if lvpen bit in bprot register is cleared. if lvpen equals zero, then lvpi is always zero and has no meaning nor effect. 0 = eeprom programming enabled 1 = eeprom programming disabled byte ?yte/other eeprom erase mode 0 = row or bulk erase mode used 1 = erase only one byte of eeprom row ?ow/all eeprom erase mode (only valid when byte = 0) 0 = all 640 bytes of eeprom erased 1 = erase only one 16-byte row of eeprom erase ?rase/normal control for eeprom 0 = normal read or program mode 1 = erase mode eelat ?eprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bus configured for programming or erasing eepgm ?eprom program command 0 = program or erase voltage switched off to eeprom array 1 = program or erase voltage switched on to eeprom array note block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. block protect register bits can be written to one (protection enabled) at any time. bulkp ?ulk erase of eeprom protect 0 = eeprom can be bulk erased normally 1 = eeprom cannot be bulk or row erased byte row action 0 0 bulk erase (all 640 bytes) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase bprot block protect $0035 bit 7 654321 bit 0 bulkp lvpen bprt4 ptcon bprt3 bprt2 bprt1 bprt0 reset: 1111111 1
motorola m68hc11 k series 24 mc6hc11kts/d lvpen ?ow voltage programming protect enable if lvpen = 1, programming of the eeprom is enabled unless the lvpi circuit detects that v dd has fallen below a safe operating voltage, thus setting the low voltage programming inhibit bit in pprog register (lvpi = 1). 0 = low voltage programming protect for eeprom disabled 1 = low voltage programming protect for eeprom enabled bprt4 ?lock protect bit for upper 128 bytes of eeprom refer to description for bprt[3:0]. ptcon ?rotect for config 0 = config register can be programmed or erased normally 1 = config register cannot be programmed or erased bprt[3:0] ?lock protect bits for eeprom 0 = protection disabled 1 = protection enabled init2 can be written only once in normal modes, any time in special modes. ee[3:0] ?eprom map position eeprom is at $xd80?xfff, where x is the hexadecimal digit represented by ee[3:0]. bits [3:0] ?ot implemented always read zero 3.5 configuration control register (config) the config register is used to define several system functions. although the config register is an address within the register block, it is actually an eeprom byte with the address of $x03f. config is made up of eeprom cells and static latches. the operation of the mcu is controlled directly by these latches and not the actual eeprom byte. when programming the config register, the eeprom byte is being accessed. when the config register is being read, the static latches are being accessed. the config register can be read at any time. the value read is the one latched from the eeprom cells during the last reset sequence. a new value programmed into this register cannot be read until a subsequent reset occurs. unused bits always read as ones. in normal modes (smod = 0), config bits can only be written using the eeprom programming se- quence, and are neither readable nor active until latched via the next reset. in special modes (smod = 1), config bits can be written at any time. bit name block protected block size bprt4 $xf80?xfff 128 bytes bprt3 $xe60?xf7f 288 bytes bprt2 $xde0?xe5f 128 bytes bprt1 $xda0?xddf 64 bytes bprt0 $xd80?xd9f 32 bytes init2 ?eprom mapping $0037 bit 7 654321 bit 0 ee3 ee2 ee1 ee0 0 0 0 0 reset: 0000000 0
m68hc11 k series motorola mc6hc11kts/d 25 romad ?om/eprom mapping control in single-chip mode romad is forced to one out of reset. 0 = rom/eprom located at $2000?7fff 1 = rom/eprom located at $a000?ffff bit 6 ?ot implemented always reads one clkx ?out clock enable 0 = xout pin disabled 1 = buffered xtal signal (four times e frequency) driven out on the xout pin paren ?ull-up assignment register enable 0 = pull-ups always disabled regardless of state of bits in ppar 1 = pull-ups either enabled or disabled through ppar nosec ?ecurity disable nosec is invalid unless the security mask option is specified before the mcu is manufactured. if se- curity mask option is omitted nosec always reads one. refer to 3.6 security feature . 0 = security enabled 1 = security disabled nocop ?op system disable resets to programmed value 0 = cop enabled (forces reset on timeout) 1 = cop disabled (does not force reset on timeout) romon ?om/eprom enable in single-chip mode, romon is forced to one out of reset. in special test mode, romon is forced to zero out of reset. 0 = rom/eprom removed from memory map 1 = rom/eprom present in memory map eeon ?eprom enable 0 = eeprom disabled from memory map 1 = eeprom present in memory map with location depending on value specified in ee[3:0] in init2 3.6 security feature the security feature protects memory contents from unauthorized access. although many devices in the m68hc11 family support the security feature, an enhancement has been added to the mc68s11k4 that protects the contents of eprom/otprom. the security feature affects how the mcu behaves in certain modes. when the optional security feature has been specified prior to manufacture and enabled via the nosec bit in config, the mcu is re- stricted to operation in single-chip modes only. when the nosec bit equals zero, the mcu ignores the state of the moda pin during reset. this allows the mcu to be operated in single-chip and bootstrap modes only. these modes of operation do not allow external visibility of the internal address and data buses. although the security feature can easily be disabled when in bootstrap mode, the bootloader firmware residing in bootstrap rom checks to see if the nosec bit is clear. if nosec is clear (security enabled), the bootloader program performs the following: config ?ystem configuration register $003f bit 7 654321 bit 0 romad 1 clkx paren nosec nocop romon eeon reset: 1
motorola m68hc11 k series 26 mc6hc11kts/d ?output $ff on sci transmitter. ?erase eeprom array. ?verify that eeprom has been erased. if it has not, repeat erase procedure. ?write $ff to every location in ram. ?check eprom for data. if data is present, stay in loop. otherwise proceed. ?erase the config register. ?continue executing bootloader routine. notice that the bootloader routine checks the eprom to see if it contains any data. the presence of data causes the routine to stay in a loop. at this time, devices with the security enhancement are only available as one-time-programmable (otp) mcus in non-windowed packages. once they have been programmed and secured, they will not function in bootstrap mode. for more information refer to m68hc11 reference manual (m68hc11rm/ad).
m68hc11 k series motorola MC68HC11Kts/d 27 4 memory expansion and chip selects two additional on-chip blocks are provided with the m68hc11 k-series mcus. the first block imple- ments additional address lines that become active only when required by the cpu. the second block provides chip-select signals that simplify the interface to external peripheral devices. both of these blocks are fully programmable by values written to associated control registers. 4.1 memory expansion new to the m68hc11 family of microcontrollers is the ability of the m68hc11 k-series mcus to extend the address range of the m68hc11 cpu beyond the physical 64 kbyte limit of the 16 cpu address lines. the following is a brief description of how the extended addressing is achieved. for a more de- tailed discussion refer to application note using the MC68HC11K4 memory mapping logic (an452/d). memory expansion is achieved by manipulating the cpu address lines such that, even though the cpu cannot distinguish more than 64 kbytes of physical memory, up to 1 mbyte can be accessed through a paged memory scheme. additional address lines xa[18:13] are provided as alternate functions of port g pins. bits in the port g assignment register (pgar) define which port g pins are to be used for mem- ory expansion address lines and which are to be used for general-purpose i/o. in order to access expanded memory, the user must first allocate a range of the 64 kbyte address space to be used for the window(s) through which external expanded memory is viewed by the cpu. the size and placement of the window(s) depend upon values written to the mmsiz and mmwbr registers, re- spectively. which bank or page of the expanded memory that is present in the window(s) at a given time is dependent upon values written to the mm1cr and mm2cr registers. up to two windows can be designated and each can be programmed to 0 (disabled), 8, 16, or 32 kbytes. the base address for each window must be an integer multiple of the window size. when the window size is 32 kbytes, the base address can be at $0000, $4000, or $8000. if the windows are defined in such a way that they overlap, bank window 1 has priority and the part of window 2 that is not overlapped by bank window 1 remains active. if a window is defined such that it overlaps any internal registers, ram, or eeprom, the portion of the registers, ram, or eeprom that is overlapped is repeated in all banks associated with that window. however, if rom/eprom is en- abled and overlapped by a window, the rom/eprom is present only in banks with xa[18:16] = 0:0:0. expanded memory is addressed by using a combination of the cpu's normal address lines addr[15:0] and the expansion address lines xa[18:13]. window size and the number of banks associated with the window determine exactly which address lines are used. the additional address lines (xa[18:13]) de- termine which bank is present in a window at a given time. the lower three expansion address lines (xa[15:13]) are used only when needed by the cpu and replace the cpu's equivalent address lines (addr[15:13]). the following tables show which address lines are used for various configurations of expanded memory. five registers control operation of the memory expansion function. mm1cr and mm2cr registers in- dicate which bank of a window is active. each contains the value to be output when the cpu selects addresses within the memory expansion window. pgar selects which pins are used for i/o or memory expansion address lines, defining which extended address lines are used. the mmwbr register de- fines the starting address of each of the two windows within the cpu 64-kbyte address range. the mm- siz register sets the size of the windows in use and selects whether the on-board general-purpose chip selects are active for cpu addresses or for expansion addresses.
motorola m68hc11 k series 28 MC68HC11Kts/d bits [7:6] ?not implemented always read zero pgar[5:0] ?ort g pin assignment bits [5:0] 0 = corresponding port g pin is general-purpose i/o 1 = corresponding port g pin is address line, xa[18:13] note a special case exists for expansion address lines xa[15:13] that overlap the cpu address lines addr[15:13]. if these lines are selected as expansion address lines in pgar, but are not used in either window, the corresponding cpu address line is output on the appropriate port g pin. mxgs[2:1] ?memory expansion select for general-purpose chip select 2 or 1 0 = general-purpose chip select 2 or 1 based on 64 kbyte cpu address 1 = general-purpose chip select 2 or 1 based on expansion address w2sz[1:0] ?window 2 size these bits select the size of memory expansion window 2. refer to the table following w1sz[1:0]. bits [3:2] ?not implemented always read zero table 5 cpu address and address expansion signals number of banks window size 8 kbytes 16 kbytes 32 kbytes 32 kbytes (window based at $4000) 2 addr[12:0] addr[13:0] addr[14:0] addr[13:0] xa13 xa14 xa15 xa[15:14] 4 addr[12:0] addr[13:0] addr[14:0] addr[13:0] xa[14:13] xa[15:14] xa[16:15] xa[16:14] 8 addr[12:0] addr[13:0] addr[14:0] addr[13:0] xa[15:13] xa[16:14] xa[17:15] xa[17:14] 16 addr[12:0] addr[13:0] addr[14:0] addr[13:0] xa[16:13] xa[17:14] xa[18:15] xa[18:14] 32 addr[12:0] addr[13:0] xa[17:13] xa[18:14] 64 addr[12:0] xa[18:13] pgar port g assignment $002d bit 7 654321 bit 0 pgar5 pgar4 pgar3 pgar2 pgar1 pgar0 reset: 0000000 0 mmsiz memory mapping size $0056 bit 7 654321 bit 0 mxgs2 mxgs1 w2sz1 w2sz0 w1sz1 w1sz0 reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 29 w1sz[1:0] ?indow 1 size these bits select the size of memory expansion window 1. w2a[15:13] ?indow 2 base address selects the three most significant bit (msb) of the base address for memory mapping window 2. refer to the table following w1a[15:13]. bit 4 ?ot implemented always reads zero w1a[15:13] ?indow base 1 address selects the three msb of the base address for memory mapping window 1. refer to the following table for additional information. bit 0 ?ot implemented always reads zero note a special case exists when the bank size is 32 kbytes and the window base ad- dress is $4000. the xa14 signal connected to the addr14 pin of the memory de- vice automatically drives an inverted cpu addr14 signal onto the xa14 pin when the window is active. the effect occurs while the cpu address is in the $4000 $bfff range, the xa pins and external physical memory range is $0000?7fff. wxsz[1:0] window size 0 0 window disabled 0 1 8 k ?indow can have up to 64 8-kbyte banks 1 0 16 k ?indow can have up to 32 16-kbyte banks 1 1 32 k ?indow can have up to 16 32-kbyte banks mmwbr memory mapping window base $0057 bit 7 654321 bit 0 $0057 w2a15 w2a14 w2a13 w1a15 w1a14 w1a13 reset: 0000000 0 msb bits window base address wxa[15:13] 8 k 16 k 32 k 0 0 0 $0000 $0000 $0000 0 0 1 $2000 $0000 $0000 0 1 0 $4000 $4000 $4000 0 1 1 $6000 $4000 $4000 1 0 0 $8000 $8000 $8000 1 0 1 $a000 $8000 $8000 1 1 0 $c000 $c000 $8000 1 1 1 $e000 $c000 $8000 mm1cr?m2cr ?emory mapping window 1 and 2 control $0058?0059 bit 7 654321 bit 0 $0058 x1a18 x1a17 x1a16 x1a15 x1a14 x1a13 mm1cr $0059 x2a18 x2a17 x2a16 x2a15 x2a14 x2a13 mm2cr reset: 00000000
motorola m68hc11 k series 30 MC68HC11Kts/d bit 7 ?not implemented always reads zero mm1cr ?memory mapping window 1 control register when a 64 kbyte cpu address falls within window 1, the value in mm1cr is driven out from the corre- sponding expansion address lines to enable the specified bank in the window. mm2cr ?memory mapping window 2 control register when a 64 kbyte cpu address falls within window 2, the value in mm2cr is driven out from the corre- sponding expansion address lines to enable the specified bank in the window. bit 0 ?not implemented always reads zero 4.2 overlap guidelines ?on-chip registers, ram, and eeprom are higher priority than expansion windows. if a window overlaps ram, registers, or eeprom, they appear in all banks at their cpu address. ?if a window overlaps on-chip rom/eprom, the rom/eprom appears only in banks with xa[18:16] = 0:0:0. ?window 1 is higher priority than window 2, therefore any overlapped portion of window 2 is inac- cessible. 4.3 chip selects m68hc11 k-series mcus have four software configured chip selects that are enabled in expanded modes. the chip select for i/o (csio) is used for i/o expansion. the program chip select (csprog ) is used with an external memory that contains the reset vectors and program. the two general-purpose chip selects, csgp1 and csgp2, are used to enable external devices. these external devices can be in the 64 kbyte memory space or in the expanded memory space. chip select signals are a shared func- tion of port h. when an mcu pin is not used for chip select functions it can be used for general-purpose i/o. the following table contains a summary of the attributes of each chip select that can be controlled by user software.
m68hc11 k series motorola MC68HC11Kts/d 31 4.3.1 program chip select (csprog ) the program chip select (csprog ) is active in the range of memory where the main program exists. csprog is enabled out of reset in all modes. after reset in normal mode, the pcs stretch select bit is set to provide one cycle of stretch so that slow memory devices can be used. 4.3.2 i/o chip select (csio) the i/o chip select (csio) is programmable for a four kbyte size located at addresses $1000 to $1fff or eight kbyte size located at addresses $0000 to $1fff. polarity of the active state is programmable for active high or active low. clock stretching can be set from zero to three cycles. csio enable ioen in csctl ? = on, off at reset (0) valid iocsa in csctl ? = address valid, 0 = e valid polarity iopl in csctl ? = active high, 0 = active low size iosz in csctl ? = 4k ($1000?1fff), 0 = 8k ($0000?1fff) start address fixed (see size) stretch io1sa:io1sb in cscstr ?, 1, 2, or 3 e clocks csprog enable pscen in csctl ? = on, on at reset valid fixed (address valid) polarity fixed (active low) size pcsza:pcszb in csctl 0:0 = 64k ($0000?ffff) 0:1 = 32k ($8000?ffff) 1:0 = 16k ($c000?ffff) 1:1 = 8k ($e000?ffff) start address fixed (see size) stretch pcsa:pcsb in cscstr ?, 1, 2, or 3 e clocks priority gcspr in csctl 1 = csgpx above csprog 0 = csprog above csgpx csgp1, csgp2 enable set size to 0k to disable valid gxpol in gpcs1c (gpcs2c) ? = address valid, 0 = e valid polarity gxav in gpcs1c (gpcs2c) ? = active high, 0 = active low size refer to gpcs1c (gpcs2c) ?k to 512k in nine steps, 0k = dis- able, can also follow memory expansion window 1 or window 2 start address refer to gpcs1a (gpcs2a) stretch refer to cscstr ?, 1, 2, or 3 e clocks other g1dg2 in gpcs1c allows csgp1 and csgp2 to be connected to an internal or gate and driven out the csgp2 pin. g1dpc in gpcs1c allows csgp1 and csprog to be connected to an internal or gate and driven out the csprog pin. g2dpc in gpcs2c allows csgp2 and csprog to be connected to an internal or gate and driven out the csprog pin. mxgs2 in mmsiz allows csgp2 to follow either 64k cpu addresses or 512k expansion addresses. mxgs1 in mmsiz allows csgp1 to follow either 64k cpu addresses or 512k expansion addresses.
motorola m68hc11 k series 32 MC68HC11Kts/d 4.3.3 general-purpose chip selects (csgp1, csgp2) the general-purpose chip selects are the most flexible and programmable and have the most control bits. polarity of active state, e valid or address valid, size, and starting address are all programmable. clock stretching can be set from zero to three cycles. each chip select can be programmed to become active whenever the cpu address enters a memory expansion window regardless of the actual bank selected. this is known as following a window. each general purpose chip select can be configured to drive the program chip select. csgp1 can be configured to drive csgp2 or the program chip select. using one chip select to drive another allows the same device to cover the address space defined by both chip selects. the two chip selects are con- nected to an internal or gate. the output of the or gate is then driven onto the pin corresponding to the driven chip select. for example, this is useful when the same external device is used with both bank windows but the windows are opened independently. in cases where one chip select drives another, determine the priority from the following table. 4.3.4 chip select priorities to minimize chip select conflicts (with one another or with internal memory and registers), the priority is determined by the gcspr bit in the csctl register. refer to the following table. 4.3.5 chip select control registers there are six chip select control registers. chip select functions are enabled by control bits in csctl register. chip selects are configured by bits in cscstr, ioen, iopl, iocsa, and iosz registers. ioen ?/o chip select enable 0 = csio disabled 1 = csio enabled iopl ?/o chip select polarity select 0 = csio active low 1 = csio active high condition priority gpcs1 drives gpcs2 gpcs1 gpcs1 drives pcs gpcs1 gpcs2 drives pcs gpcs2 gpcs1 and gpcs2 drive pcs gpcs1 gcspr = 0 gcspr = 1 on-chip registers on-chip registers on-chip ram on-chip ram bootloader rom bootloader rom on-chip eeprom on-chip eeprom on-chip rom/eprom on-chip rom/eprom i/o chip select i/o chip select program chip select gp chip select 1 gp chip select 1 gp chip select 2 gp chip select 2 program chip select csctl chip select control $005b bit 7 654321 bit 0 ioen iopl iocsa iosz gcspr pcsen pcsza pcszb reset: 0000010 0
m68hc11 k series motorola MC68HC11Kts/d 33 iocsa ?/o chip select address valid 0 = valid during e-clock high time 1 = valid during address valid time iosz ?/o chip select size select 0 = $1000?1fff (4 kbyte) 1 = $0000?1fff (8 kbyte) gcspr ?eneral-purpose chip select priority 0 = program chip select has priority over general-purpose chip selects 1 = general-purpose chip selects have priority over program chip select pcsen ?rogram chip select enable 0 = csprog disabled 1 = csprog enabled pcsza, pcszb ?rogram chip select size (a or b) iosa, iosb ?sio stretch select gp1sa, gp1sb ?sgp1 stretch select gp2sa, gp2sb ?sgp2 stretch select pcsa, pcsb ?sprog stretch select g1a[18:11] ?eneral-purpose chip select 1 address selects the starting address of general-purpose chip select 1 range. refer to the g1sza?1szd table. pcsza pcszb size (bytes) address range 0 0 64 k $0000?ffff 0 1 32 k $8000?ffff 1 0 16 k $c000?ffff 1 1 8 k $e000?ffff cscstr ?hip select clock stretch $005a bit 7 654321 bit 0 iosa iosb gp1sa gp1sb gp2sa gp2sb pcsa pcsb reset: 00000001 normal modes 00000000 special modes bit [a:b] clock stretch 0 0 none 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles gpcs1a ?eneral-purpose chip select 1 address $005c bit 7 654321 bit 0 g1a18 g1a17 g1a16 g1a15 g1a14 g1a13 g1a12 g1a11 reset: 0000000 0
motorola m68hc11 k series 34 MC68HC11Kts/d g1dg2 ?eneral-purpose chip select 1 drives general-purpose chip select 2 0 = csgp1 does not affect csgp2 1 = csgp1 and csgp2 are connected to an or gate and driven out csgp2 g1dpc ?eneral-purpose chip select 1 drives program chip select 0 = csgp1 does not affect csprog 1 = csgp1 and csprog are connected to an or gate and driven out csprog g1pol ?eneral-purpose chip select 1 polarity select 0 = csgp1 active low 1 = csgp1 active high g1av ?eneral-purpose chip select 1 address valid select 0 = csgp1 active during e high time 1 = csgp1 active during address valid time g1sza?1szd ?eneral-purpose chip select 1 size g2a[18:11] ?eneral-purpose chip select 2 address selects the starting address of general-purpose chip select 2 range. refer to g2sza?2szd table. gpcs1c ?eneral-purpose chip select 1 control $005d bit 7 654321 bit 0 g1dg2 g1dpc g1pol g1av g1sza g1szb g1szc g1szd reset: 0000000 0 g1szx valid bits valid bits abcd size (bytes) (mxgs1 = 0) (mxgs1 = 1) 0000 disabled none none 0001 2 k addr[15:11] g1a[18:11] 0010 4 k addr[15:12] g1a[18:12] 0011 8 k addr[15:13] g1a[18:13] 0100 16 k addr[15:14] g1a[18:14] 0101 32 k addr15 g1a[18:15] 0110 64 k none g1a[18:16] 0111 128 k none g1a[18:17] 1000 256 k none g1a18 1001 512 k none none 1010 follow window 1 none none 1011 follow window 2 none none 1100?111 default to 512 k none none gpcs2a ?eneral-purpose chip select 2 address $005e bit 7 654321 bit 0 g2a18 g2a17 g2a16 g2a15 g2a14 g2a13 g2a12 g2a11 reset: 0000000 0 gpcs2c ?eneral-purpose chip select 2 control $005f bit 7 654321 bit 0 g2dpc g2pol g2av g2sza g2szb g2szc g2szd reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 35 bit 7 ?not implemented always reads zero g2dpc ?general-purpose chip select 2 drives program chip select 0 = csgp2 does not affect csprog 1 = csgp2 and csprog are connected to an or gate and driven out csprog g2pol ?general-purpose chip select 2 polarity select 0 = csgp2 active low 1 = csgp2 active high g2av ?general-purpose chip select 2 address valid select 0 = active during e high time 1 = active during address valid time g2sza?2szd ?general-purpose chip select 2 size 4.3.6 examples of memory expansion using chip selects on the following two pages are examples of memory expansion schemes that use chip select signals to simplify the interface to the external memory devices. although schematics are not provided, careful study of the memory map diagram for each example will reveal the simplicity with which an expanded system can be created. both examples require a minimum of external circuitry as well as very little pro- gram code. this example is a system consisting of the mcu and a single 27c512-type memory device. this system uses one chip select and has one window containing eight banks of eight kbytes each. in this example, a total of 64 kbytes is added to the address range of the mcu. three of the expansion address lines (xa[15:13]) are used. register values particular to this example are given below the diagram. g2szx valid bits valid bits abcd size (bytes) (mxgs2 = 0) (mxgs2 = 1) 0000 disabled none none 0001 2 k addr[15:11] g2a[18:11] 0010 4 k addr[15:12] g2a[18:12] 0011 8 k addr[15:13] g2a[18:13] 0100 16 k addr[15:14] g2a[18:14] 0101 32 k addr15 g2a[18:15] 0110 64 k none g2a[18:16] 0111 128 k none g2a[18:17] 1000 256 k none g2a18 1001 512 k none none 1010 follow window 1 none none 1011 follow window 2 none none 1100?111 default to 512 k none none
motorola m68hc11 k series 36 MC68HC11Kts/d figure 7 memory expansion example 1 this example is a system consisting of the mcu, a single 27c512-type memory device as in the previ- ous example, and two 6226-type memory devices as well. this system uses two chip selects and has two windows. for purposes of explanation, the setup of the first window is identical to the previous ex- ample. in addition, a second window consisting of 16 banks of 16 kbytes each uses the second chip select signal. window 1 contains 64 kbytes of expanded memory pages, window 2 contains a total of 256 kbytes of expanded memory. a total of five expansion address lines are used. register values par- ticular to this example are given below the diagram. $0000 $1000 $4000 $6000 $00000 $01fff $02000 $03fff $04000 $05fff $06000 $07fff $08000 $09fff $0a000 $0bfff $0c000 $0dfff $0e000 $0ffff internal eprom chip select 1 $ffff window 1 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= pgar = $07 mmwbr = $04 mmsiz = $41 xa[15:13] window 1 @ $4000, window 2 disabled window 1 = 8 kbytes, window 2 disabled csctl = $00 gpcs1a = $00 gpsc1c = $06 gpcs2a = $00 gpcs2c = $00 no i/o or program chip selects gen. purpose chip select 1 from $00000 64 kbyte range (8 x 8k) n/a gen. purpose chip select 2 disabled $a000
m68hc11 k series motorola MC68HC11Kts/d 37 figure 8 memory expansion example 2 pgar = $1f mmwbr = $84 mmsiz = $e1 xa[17:13] window 1 @ $4000, window 2 @ $8000 window 1 = 8 kbytes, window 2 = 16 kbytes csctl = $00 gpcs1a = $00 gpsc1c = $06 gpcs2a = $00 gpcs2c = $08 no i/o or program chip selects gen. purpose chip select 1 from $00000 64 kbyte range (8 x 8k) gen. purpose chip select 2 from $00000 256 kbyte range (16 x 16k) $0000 $1000 $4000 $8000 $00000 $01fff $02000 $03fff $04000 $05fff $06000 $07fff $08000 $09fff $0a000 $0bfff $0c000 $0dfff $0e000 $0ffff internal eprom chip select 1 $ffff window 1 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= xa[15:13]= $a000 $00000 $03fff $04000 $07fff $08000 $0bfff $0c000 $0ffff $10000 $13fff $3c000 $3ffff window 2 bank 0 bank 1 bank 2 bank 3 bank 4 bank 15 0:0:0:0 0:0:0:1 0:0:1:0 0:0:1:1 0:1:0:0 1:1:1:1 xa[17:14]= xa[17:14]= xa[17:14]= xa[17:14]= xa[17:14]= xa[17:14]= chip select 2 ? ? ? ? ? ? $6000 $c000 ee/reg/ram
motorola m68hc11 k series 38 MC68HC11Kts/d 5 resets and interrupts all m68hc11 mcus have three reset vectors and 18 interrupt vectors. the reset vectors are as follows: ?reset , or power-on reset ?clock monitor fail ?cop failure the 18 interrupt vectors service 22 interrupt sources (three nonmaskable, 19 maskable). the three non- maskable interrupt sources are as follows: ?xirq pin (x-bit interrupt) ?illegal opcode trap ?software interrupt on-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter- rupt mask bit (i) in the condition code register (ccr) is clear. maskable interrupts are prioritized accord- ing to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (hprio). the hprio register can be written at any time, provided bit i in the ccr is set. nineteen interrupt sources in the m68hc11 k series devices are subject to masking by the global inter- rupt mask bit (bit i in the ccr). in addition to the global bit i, all of these sources, except the external interrupt (irq ) pin, are controlled by local enable bits in control registers. most interrupt sources in m68hc11 devices have separate interrupt vectors; therefore, there is usually no need for software to poll control registers to determine the cause of an interrupt. for some interrupt sources, such as the sci interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. for example, the rdrf flag in the sci system is cleared by the automatic clearing mechanism invoked by a read of the sci status register while rdrf is set, followed by a read of the sci data register. the normal response to an rdrf interrupt request would be to read the sci status register to check for receive errors, then to read the received data from the sci data register. these two steps satisfy the automatic clearing mechanism without requiring any special instructions. refer to the following table for a list of interrupt and reset vector assignments.
m68hc11 k series motorola MC68HC11Kts/d 39 *same level as an instruction *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. adpu ?/d converter power up refer to 9 analog-to-digital converter . csel ?lock select refer to 9 analog-to-digital converter . irqe ?rq select edge sensitive only 0 = low level recognition 1 = falling edge recognition dly ?nable oscillator start-up delay on exit from stop 0 = no stabilization delay on exit from stop 1 = stabilization delay enabled on exit from stop vector address interrupt source ccr mask bit local mask priority (1 = high) ffc0, c1 ?fd4, d5 reserved ffd6, d7 sci serial system i sci receive data register full rie 19 sci receiver overrun rie 20 sci transmit data register empty tie 21 sci transmit complete tcie 22 sci idle line detect ilie 23 ffd8, d9 spi serial transfer complete i spie 18 ffda, db pulse accumulator input edge i paii 17 ffdc, dd pulse accumulator overflow i paovi 16 ffde, df timer overflow i toi 15 ffe0, e1 timer input capture 4/output compare 5 i i4/o5i 14 ffe2, e3 timer output compare 4 i oc4i 13 ffe4, e5 timer output compare 3 i oc3i 12 ffe6, e7 timer output compare 2 i oc2i 11 ffe8, e9 timer output compare 1 i oc1i 10 ffea, eb timer input capture 3 i ic3i 9 ffec, ed timer input capture 2 i ic2i 8 ffee, ef timer input capture 1 i ic1i 7 fff0, f1 real time interrupt i rtii 6 fff2, f3 irq i none 5 fff4, f5 xirq pin x none 4 fff6, f7 software interrupt none none * fff8, f9 illegal opcode trap none none * fffa, fb cop failure none nocop 3 fffc, fd clock monitor fail none cme 2 fffe, ff reset none none 1 option ?ystem configuration options $0039 bit 7 654321 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0001000 0
motorola m68hc11 k series 40 MC68HC11Kts/d cme ?lock monitor enable 0 = clock monitor disabled; slow clocks can be used 1 = slow or stopped clocks cause clock failure reset fcme ?orce clock monitor enable 0 = clock monitor follows the state of the cme bit 1 = clock monitor circuit is enabled until next reset cr[1:0] ?op timer rate select refer to nocop bit in config register. write $55 (%01010101) to coprst to arm cop watchdog clearing mechanism. write $aa (%10101010) to coprst to reset cop watchdog. refer to nocop bit in config register. *rboot, smod, and mda reset depend on power-up initialization mode and can only be written in special mode. rboot ?ead bootstrap rom refer to 2 operating modes . smod ?pecial mode select refer to 2 operating modes . mda ?ode select a refer to 2 operating modes . table 6 cop timer rate select (timeout period length) cr[1:0] rate selected xtal = 8.0 mhz timeout ? ms, +16.4 ms xtal = 12.0 mhz timeout ? ms, +10.9 ms xtal = 16.0 mhz timeout ? ms, +8.2 ms 0 0 2 15 16.384 ms 10.923 ms 8.192 ms 0 1 2 17 65.536 ms 43.691 ms 32.768 ms 1 0 2 19 262.14 ms 174.76 ms 131.07 ms 1 1 2 21 1.049 sec 699.05 ms 524.29 ms e = 2.0 mhz 3.0 mhz 4.0 mhz coprst ?rm/reset cop timer circuitry $003a bit 7 654321 bit 0 7654321 0 reset: 0000000 0 hprio ?ighest priority i-bit interrupt and miscellaneous $003c bit 7 654321 bit 0 rboot* smod* mda* psel4 psel3 psel2 psel1 psel0 reset: 0011 0
m68hc11 k series motorola MC68HC11Kts/d 41 psel[4:0] ?riority select bit 4 through bit 0 can be written only while the i-bit in the ccr is set (interrupts disabled). these bits select one interrupt source to be elevated above all other i-bit related sources. pselx 43210 interrupt source promoted 0 0 0 x x reserved (default to irq ) 00100 reserved (default to irq ) 00101 reserved (default to irq ) 00110irq 00111 real-time interrupt 01000 timer input capture 1 01001 timer input capture 2 01010 timer input capture 3 01011 timer output compare 1 01100 timer output compare 2 01101 timer output compare 3 01110 timer output compare 4 01111 timer output compare 5/input capture 4 10000 timer overflow 10001 pulse accumulator overflow 10010 pulse accumulator input edge 10011 spi serial transfer complete 10100 sci serial system 10101 reserved (default to irq ) 10110 reserved (default to irq ) 10111 reserved (default to irq ) 1 1 x x x reserved (default to irq )
motorola m68hc11 k series 42 MC68HC11Kts/d 6 parallel input/output m68hc11 k-series mcus have up to 62 input/output lines, depending on the operating mode. to en- hance the i/o functions, the data bus of this microcontroller is nonmultiplexed. the following table is a summary of the configuration and features of each port. note port pin function is mode dependent. do not confuse pin function with the electrical state of the pin at reset. port pins are either driven to a specified logic level or are configured as high impedance inputs. i/o pins configured as high-impedance in- puts have port data that is indeterminate. the contents of the corresponding latch- es are dependent upon the electrical state of the pins during reset. in port descriptions, an "i" indicates this condition. port pins that are driven to a known log- ic level during reset are shown with a value of either one or zero. some control bits are unaffected by reset. reset states for these bits are indicated with a "u". note to enable pa3 as fourth input capture, set the i4/o5 bit in the pactl register. oth- erwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the dda3 bit is set (configuring pa3 as an output), and ic4 is enabled, writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/o5 register is acting as ic4. pa7 drives the pulse ac- cumulator input but also can be configured for general-purpose i/o or output com- pare. note that even when pa7 is configured as an output, the pin still drives the pulse accumulator input. dda[7:0] ?ata direction for port a 0 = corresponding pin configured for input 1 = corresponding pin configured for output port input pins output pins bidirectional pins shared functions port a 8 timer port b 8 high order address port c 8 data bus port d 6 sci and spi port e 8 a/d converter port f 8 low order address port g 8 memory expansion port h 8 pwm, chip select porta ?ort a data $0000 bit 7 654321 bit 0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: iiiiiii i alt. pin func.: pai oc2 oc3 oc4 ic4/oc5 ic1 ic2 ic3 and/or: oc1 oc1 oc1 oc1 oc1 ddra ?ata direction register for port a $0001 bit 7 654321 bit 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 43 reset state is mode dependent. in single-chip or bootstrap modes, port b pins are high-impedance in- puts with selectable internal pull-up resistors. in expanded or test modes, port b pins are high order ad- dress outputs and portb is not in the memory map. ddb[7:0] ?ata direction for port b 0 = corresponding pin configured for input 1 = corresponding pin configured for output reset state is mode dependent. in single-chip or bootstrap modes, port c pins are high-impedance in- puts with selectable internal pull-up resistors. in expanded or test modes, port c pins are data bus inputs and outputs and portc is not in the memory map. refer to cwom bit in opt2 register description that follows. ddc[7:0] ?ata direction for port c. refer to cwom bit in opt2 register description that follows. 0 = corresponding pin configured for input 1 = corresponding pin configured for output portb ?ort b data $0004 bit 7 654321 bit 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 s. chip or boot: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: iiiiiii i expan. or test: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 ddrb ?ata direction register for port b $0002 bit 7 654321 bit 0 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 reset: 0000000 0 portc ?ort c data $0006 bit 7 654321 bit 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 s. chip or boot: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0000000 0 expan. or test: data7 data6 data5 data4 data3 data2 data1 data0 ddrc ?ata direction register for port c $0007 bit 7 654321 bit 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 reset: 0000000 0
motorola m68hc11 k series 44 MC68HC11Kts/d lirdv?ir driven refer to 2 operating modes . cwom ?ort c wired-or mode 0 = port c operates normally. 1 = port c outputs are open-drain. bit 5 ?ot implemented always read zero irvne ?nternal read visibility/not e refer to 2 operating modes . lsbf ?pi lsb first enable refer to 8 serial peripheral interface . spr2 ?pi clock (sck) rate select refer to 8 serial peripheral interface . xdv[1:0] ?out clock divide select refer to 2 operating modes . bits [7:6] ?not implemented always read zero ddd[5:0] ?data direction for port d 0 = corresponding pin configured for input 1 = corresponding pin configured for output note when the spi system is in slave mode, ddd5 has no meaning nor effect. when the spi system is in master mode, ddd5 determines whether bit 5 of portd is an error detect input (ddd5 = 0) or a general-purpose output (ddd5 = 1). if the spi system is enabled and expects any of bits [4:2] to be an input that bit will be an input regardless of the state of the associated ddr bit. if any of bits [4:2] are expected to be outputs that bit will be an output only if the associated ddr bit is set. opt2 ?ystem configuration options 2 $0038 bit 7 654321 bit 0 lirdv cwom irvne lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0 portd ?ort d data $0008 bit 7 654321 bit 0 pd5 pd4 pd3 pd2 pd1 pd0 reset: 0 0 iiiii i alt. pin func.: ss sck mosi miso txd rxd ddrd ?ata direction register for port d $0009 bit 7 654321 bit 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 45 spie ?pi interrupt enable refer to 8 serial peripheral interface . spe ?pi system enable refer to 8 serial peripheral interface . dwom ?ort d wired-or mode option for spi pins pd[5:2] (see also woms bit in sccr1) 0 = pd[5:2] are normal cmos outputs 1 = pd[5:2] are open-drain outputs mstr ?aster/slave mode select refer to 8 serial peripheral interface . cpol ?lock polarity refer to 8 serial peripheral interface . cpha ?lock phase refer to 8 serial peripheral interface . spr[1:0] ?pi clock rate selects refer to 8 serial peripheral interface . loops ?ci loop mode enable refer to 7 serial communications interface . woms ?ort d wired-or mode option for spi pins pd[5:2] (see also dwom bit in spcr.) 0 = txd and rxd operate normally 1 = txd and rxd are open drains if operating as an output bit 5 ?ot implemented always reads zero m ?ode (select character format) refer to 7 serial communications interface . wake ?akeup by address mark/idle refer to 7 serial communications interface . ilt ?dle line type refer to 7 serial communications interface . pe ?arity enable refer to 7 serial communications interface . spcr ?erial peripheral control $0028 bit 7 654321 bit 0 spie spe dwom mstr cpol cpha spr1 spr0 reset: 00100000 boot mode 00000000 other modes sccr1 ?ci control 1 $0072 bit 7 654321 bit 0 loops woms m wake ilt pe pt reset: 01000000 boot mode 00000000 other modes
motorola m68hc11 k series 46 MC68HC11Kts/d pt ?arity type refer to 7 serial communications interface . ddf[7:0] ?ata direction for port f 0 = corresponding pin configured for input 1 = corresponding pin configured for output reset state is mode dependent. in single-chip or bootstrap modes, port f is high-impedance input with selectable internal pull-up resistors. in expanded or test modes, port f pins are low order address out- puts and portf is not in the memory map. port h pins reset to high-impedance inputs with selectable internal pull-up resistors. in expanded and special test modes, reset also causes ph7 to be configured as csprog . ddh[7:0] ?ata direction for port h 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output porte ?ort e data $000a bit 7 654321 bit 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: iiiiiiii alt. pin func.: an7 an6 an5 an4 an3 an2 an1 an0 ddrf ?ata direction register for port f $0003 bit 7 654321 bit 0 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0000000 0 portf ?ort f data $0005 bit 7 654321 bit 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 s. chip or boot: pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: iiiiiii i expan. or test: addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 porth ?ort h data $007c bit 7 654321 bit 0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 reset: iiiiiii i alt. pin func.: csprog csgp2 csgp1 csio pw4 pw3 pw2 pw1 ddrh ?ata direction register for port h $007d bit 7 654321 bit 0 ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 47 note in expanded and special test modes, chip-select circuitry forces the i/o state to be an output for each port h pin associated with an enabled chip select. in any mode, pwm circuitry forces the i/o state to be an output for each port h line associated with an enabled pulse width modulator channel. in these cases, data direction bits are not changed and have no effect on these lines. ddrh reverts to controlling the i/o state of a pin when the associated function is disabled. refer to 4.3 memory expansion and chip selects and 12 pulse-width modulation timer for further information. port g pins reset to high-impedance inputs with selectable internal pull-up resistors. in expanded and special test modes pg7 becomes r/w . refer to pgar register description. ddg[7:0] ?ata direction for port g 0 = configure corresponding i/o pin for input only 1 = configure corresponding i/o pin for output in expanded and test modes, bit 7 is configured for r/w , forcing the state of this pin to be an output although the ddrg value remains zero. refer to pgar register description. bits [7:6] ?ot implemented always read zero pgar[5:0] ?ort g pin assignment bits [5:0] 0 = corresponding port g pin is general-purpose i/o 1 = corresponding port g pin is memory expansion address line (xa[18:13]) note each pgar bit forces the i/o state to be an output for each port g pin associated with an enabled expansion address line. in this case, data direction bits are not changed and have no effect on these lines. ddrg reverts to controlling the i/o state of a pin when the associated function is disabled. refer to 4.1 memory ex- pansion for further information. portg ?ort g data $007e bit 7 654321 bit 0 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 reset: iiiiiii i alt. pin func.: r/w xa18 xa17 xa16 xa15 xa14 xa13 ddrg ?ata direction register for port g $007f bit 7 654321 bit 0 ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 reset: 0000000 0 pgar port g assignment $002d bit 7 654321 bit 0 $ 0 02d pgar5 pgar4 pgar3 pgar2 pgar1 pgar0 reset: 0000000 0
motorola m68hc11 k series 48 MC68HC11Kts/d bits [7:4] ?ot implemented always read zero xppue ?ort x pin pull-up enable valid only when paren = 1. refer to paren bit in the config register description. 0 = port x pin on-chip pull-up devices disabled 1 = port x pin on-chip pull-up devices enabled note fppue and bppue have no effect in expanded mode because port f and port b are address outputs. ppar ?ort pull-up assignment $002c bit 7 654321 bit 0 hppue gppue fppue bppue reset: 0000111 1
m68hc11 k series motorola MC68HC11Kts/d 49 7 serial communications interface the sci, a universal asynchronous receiver transmitter (uart) serial communications interface, is one of two independent serial i/o subsystems in m68hc11 k-series mcus. rearranging registers and con- trol bits used in previous m68hc11 family devices has enhanced the existing sci system and added new features, which include the following: ? a 13-bit modulus prescaler that allows greater baud rate control ? a new idle mode detect, independent of preceding serial data ? a receiver active flag ? hardware parity for both transmitter and receiver the enhanced baud rate generator is shown in the following diagram. refer to table 7 for standard val- ues. figure 9 sci baud generator circuit diagram 13-bit counter 13-bit compare scbdh/l sci baud control internal phase 2 clock = ? 2 synch ? 16 receiver baud rate clock transmitter baud rate clock extal reset
motorola m68hc11 k series 50 MC68HC11Kts/d figure 10 sci transmitter block diagram fe nf or idle rdrf tc tdre scsr interrupt status sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd scdr tx buffer transfer tx buffer shift enable jam enable preamble?am 1s break?am 0s (write only) force pin direction (out) size 8/9 wake m t8 r8 sccr1 sci control 1 transmitter baud rate clock 8 8 8
m68hc11 k series motorola MC68HC11Kts/d 51 figure 11 sci receiver block diagram fe nf or idle rdrf tc tdre scsr1 sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m woms loops wake-up logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0/ rxd scdrl tx/rx data low stop (8)76543210 10 (11) - bit rx shift register (read-only) sccr1 sci control 1 rie rdrf start msb all ones data recovery ? 16 rwu re m disable driver pe ilt pt pf raf parity detect scsr2 sci status 2 receiver baud rate clock 7 6 5 4 3 2 1 0 scdrh tx/rx data high r8 t8 ? ? ? ? ? $x076 $x077
motorola m68hc11 k series 52 MC68HC11Kts/d btst ?aud register test (test) factory test only bspl ?aud rate counter split (test) factory test only bit 5 ?ot implemented always reads zero sbr[12:0] ?ci baud rate selects use the following formula to calculate sci baud rate. refer to the table of baud rate control values for example rates. sci baud rate = extal ? [16 * (2 * br)] where br is the contents of scbdh/l (br = 1, 2, 3 ... 8191). br = 0 disables the baud rate generator. scbdh/l ?ci baud rate control high/low $0070, $0071 bit 7 654321 bit 0 $0070 btst bspl sbr12 sbr11 sbr10 sbr9 sbr8 high reset: 00000000 $0071 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 low reset: 00000100 table 7 sci baud rate control values target crystal frequency (extal) baud 8 mhz 12 mhz 16 mhz rate dec value hex value dec value hex value dec value hex value 110 2272 $08e0 3409 $0d51 4545 $11c1 150 1666 $0682 2500 $09c4 3333 $0d05 300 833 $0341 1250 $04e2 1666 $0682 600 416 $01a0 625 $0271 833 $0341 1200 208 $00d0 312 $0138 416 $01a0 2400 104 $0068 156 $009c 208 $00d0 4800 52 $0034 78 $004e 104 $0068 9600 26 $001a 39 $0027 52 $0034 19.2 k 13 $000d 20 $0014 26 $001a 38.4 k 13 $000d sccr1 ?ci control 1 $0072 bit 7 654321 bit 0 loops woms m wake ilt pe pt reset: 01000000 bootstrap mode 00000000 other modes
m68hc11 k series motorola MC68HC11Kts/d 53 loops ?ci loop mode enable 0 = sci transmit and receive operate normally 1 = sci transmit and receive are disconnected from txd and rxd pins, and transmitter output is fed back into the receiver input woms ?ired-or mode option for pd[1:0] (see also dwom bit in spcr.) 0 = txd and rxd operate normally 1 = txd and rxd are open drains if operating as an output bit 5 ?ot implemented always reads zero m ?ode (select character format) 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ?akeup by address mark/idle 0 = wakeup by idle line recognition 1 = wakeup by address mark (most significant data bit set) ilt ?dle line type 0 = short (sci counts consecutive ones after start bit) 1 = long (sci counts ones only after stop bit) pe ?arity enable 0 = parity disabled 1 = parity enabled pt ?arity type 0 = parity even (even number of ones causes parity bit to be zero, odd number of ones causes par- ity bit to be one) 1 = parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity bit to be one) tie ?ransmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ?ransmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ?eceiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ?dle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ?ransmitter enable 0 = transmitter disabled 1 = transmitter enabled sccr2 ?ci control 2 $0073 bit 7 654321 bit 0 tie tcie rie ilie te re rwu sbk reset: 0000000 0
motorola m68hc11 k series 54 MC68HC11Kts/d re ?eceiver enable 0 = receiver disabled 1 = receiver enabled rwu ?eceiver wakeup control 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ?end break 0 = break generator off 1 = break codes generated as long as sbk = 1 tdre ?ransmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr1 and then writing to scdr. 0 = scdr busy 1 = scdr empty tc ?ransmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr1 and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ?eceive data register full flag rdrf is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr1 and then reading scdr. 0 = scdr empty 1 = scdr full idle ?dle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr1 and then reading scdr. 0 = rxd line is active 1 = rxd line is idle or ?verrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr1 and then reading scdr. 0 = no overrun 1 = overrun detected nf ?oise error flag nf is set if majority sample logic detects anything other than a unanimous decision. clear nf by reading scsr1 and then reading scdr. 0 = unanimous decision 1 = noise detected fe ?raming error fe is set when a zero is detected where a stop bit was expected. clear the fe flag by reading scsr1 and then reading scdr. 0 = stop bit detected 1 = zero detected scsr1 ?ci status register 1 $0074 bit 7 654321 bit 0 tdre tc rdrf idle or nf fe pf reset: 1100000 0
m68hc11 k series motorola MC68HC11Kts/d 55 pf ?arity error flag pf is set if received data has incorrect parity. clear pf by reading scsr1 and then reading scdr. 0 = parity correct 1 = incorrect parity detected bits [7:1] ?ot implemented always read zero raf ?eceiver active flag (read only) 0 = a character is not being received 1 = a character is being received r8 ?eceiver bit 8 ninth serial data bit received when sci is configured for nine-data-bit operation. t8 ?ransmitter bit 8 ninth serial data bit transmitted when sci is configured for nine-data-bit operation. bits [5:0] ?ot implemented always read zero r/t[7:0] ?eceiver/transmitter data bits [7:0] sci data is double buffered in both directions. scsr2 ?ci status register 2 $0075 bit 7 654321 bit 0 raf reset: 0000000 0 scdrh, scdrl ?ci data register high/low $0076, $0077 bit 7 654321 bit 0 $0076 r8 t8 scdrh (high) $0077 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdrl (low)
motorola m68hc11 k series 56 MC68HC11Kts/d 8 serial peripheral interface the spi allows the mcu to communicate synchronously with peripheral devices and other micropro- cessors. data rates can be as high as 2 mbits per second when configured as a master and 4 mbits per second when configured as a slave (assuming 4 mhz bus speed). two control bits in opt2 allow the transfer of data either msb or lsb first and select an additional divide by four stage to be inserted before the spi baud rate clock divider. figure 12 spi block diagram lsbf options register 2 internal mcu clock divider select spi clock (master) 8-bit shift register read data buffer msb clock logic s m m s pin control logic miso/ pd2 mosi/ pd3 sck/ pd4 ss / pd5 m s mstr spe dwom spr0 mstr spe spie spie spe dwom mstr cpha cpol spr1 spr0 spcr spi control register spif wcol modf spsr spi status register spi control internal data bus spi interrupt request ? 2 ? 4 ? 16 ? 32 ? 8 ? 16 ? 64 ? 128 lsbf 8 8 8 spr1 spr2 lsb clock
m68hc11 k series motorola MC68HC11Kts/d 57 spie ?erial peripheral interrupt enable 0 = spi interrupts disabled 1 = spi interrupts enabled spe ?erial peripheral system enable 0 = spi off 1 = spi on dwom ?ort d wired-or mode option for spi pins pd[5:2] (see also woms bit in sccr1.) 0 = normal cmos outputs 1 = open-drain outputs mstr ?aster mode select 0 = slave mode 1 = master mode cpol, cpha ?lock polarity, clock phase refer to the following figure, spi transfer format . figure 13 spi transfer format note this figure shows transmission order when lsbf = 0 default. if lsbf = 1, data is transferred in reverse order (lsb first). spcr ?erial peripheral control register $0028 bit 7 654321 bit 0 spie spe dwom mstr cpol cpha spr1 spr0 reset: 000001uu 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # (for reference) ss (to slave) 654321 lsb msb msb654321lsb sample input data out sample input data out (cpha = 1) (cpha = 0)
motorola m68hc11 k series 58 MC68HC11Kts/d spr[2:0] ?pi clock rate selects (spr2 is located in opt2 register) spif ?pi transfer complete flag this flag is set when an spi transfer is complete (after eight sck cycles in a data transfer). clear this flag by reading spsr, then access spdr. 0 = no spi transfer complete or spi transfer still in progress 1 = spi transfer complete wcol ?rite collision error flag this flag is set if the mcu tries to write data into spdr while an spi data transfer is in progress. clear this flag by reading spsr, then access spdr. 0 = no write collision error 1 = spdr written while spi transfer in progress bit 5 ?ot implemented always reads zero modf ?ode fault (mode fault terminates spi operation) set when ss is pulled low while mstr = 1. cleared by spsr read followed by spcr write. 0 = no mode fault error 1 = ss pulled low in master mode bits [3:0] ?ot implemented always read zero spi is double buffered in, single buffered out. table 8 spi clock rate selects spr[2:0] divide e clock by frequency at e = 2 mhz (baud) frequency at e = 3 mhz (baud) frequency at e = 4 mhz (baud) 0 0 0 2 1.0 mhz 3.0 mhz 4.0 mhz 0 0 1 4 500 khz 750 khz 1.0 mhz 0 1 0 16 125 khz 187.5 khz 250 khz 0 1 1 32 62.5 khz 93.75 khz 125 khz 1 0 0 8 250 khz 375 khz 500 khz 1 0 1 16 125 khz 187.5 khz 250 khz 1 1 0 64 31.25 khz 46.875 khz 62.5 khz 1 1 1 128 15.625 khz 23.438 khz 31.25 khz spsr ?erial peripheral status register $0029 bit 7 654321 bit 0 spif wcol modf reset: 00000000 spdr ?pi data $002a bit 7 654321 bit 0 bit 7 654321 bit 0
m68hc11 k series motorola MC68HC11Kts/d 59 lirdv?ir driven refer to 2 operating modes . cwom ?ort c wired-or mode refer to 6 parallel input/output . bit 5 ?ot implemented always read zero irvne ?nternal read visibility/not e refer to 2 operating modes . lsbf ?pi lsb first enable 0 = spi data transferred msb first 1 = spi data transferred lsb first spr2 ?pi clock (sck) rate select adds a divide by four prescaler to spi clock chain. refer to spcr register. xdv[1:0] ?out clock divide select refer to 2 operating modes . opt2 ?ystem configuration options 2 $0038 bit 7 654321 bit 0 lirdv cwom irvne lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0
motorola m68hc11 k series 60 MC68HC11Kts/d 9 analog-to-digital converter the analog-to-digital (a/d) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. the a/d converter system contained in m68hc11 k-series mcus is an 8-channel,8-bit, multiplexed-input, successive-approximation converter. it does not require external sample and hold circuits. the clock source for the a/d converter? charge pump, like the clock source for the eeprom charge pump, is selected with the csel bit in the option register. when the e clock is slower than 1 mhz, the csel bit must be set to ensure that the successive approximation sequence for the a/d converter will be completed before any charge loss occurs. in the case of the eeprom, it is the efficiency of the charge pump that is affected. figure 14 a/d converter block diagram the a/d converter can operate in single or multiple conversion modes. multiple conversions are per- formed in sequences of four. sequences can be performed on a single channel or an a group of chan- nels. dedicated lines v rh and v rl provide the reference supply voltage inputs. pe0/ an0 pe1/ an1 pe2/ an2 pe3/ an3 analog mux 8-bit capacitive dac with sample and hold successive approximation register and control adctl a/d control cb cc cd mult scan ccf ca addr 3 a/d result 3 result register interface result internal data bus v rh v rl addr 4 a/d result 4 addr 2 a/d result 2 addr 1 a/d result 1 pe4/ an4 pe5/ an5 pe6/ an6 pe7/ an7
m68hc11 k series motorola MC68HC11Kts/d 61 a multiplexer allows the single a/d converter to select one of 16 analog input signals. the a/d converter control logic implements automatic conversion sequences on a selected channel four times or on four channels once each. a write to the adctl register initiates conversions and, if made while a conversion is in progress, a write to adctl also halts that conversion operation, sets ccf, and proceeds to the next instruction. when the scan bit is zero, four requested conversions are performed, once each, to fill the four result registers. when scan is one, conversions continue in a round-robin fashion with the result registers being updated as new data becomes available. when the mult bit is zero, the a/d converter system is configured to perform conversions on each channel in the group of four channels specified by the cd and cc channel select bits. figure 15 timing diagram for a sequence of four a/d conversions figure 16 electrical model of an analog input pin (sample mode) msb 4 cycles e clock write bit 6 2 cyc bit 5 2 cyc bit 4 2 cyc bit 3 2 cyc bit 2 2 cyc bit 1 2 cyc lsb 2 cyc end 12 e cycles sample analog input successive approximation sequence 2 cyc convert fourth channel and update addr4 convert third channel and update addr3 convert second channel and update addr2 convert first channel and update addr1 set repeat e cycles 128 96 64 32 0 to adctl sequence if scan = 1 ccf flag dac capacitance v rl analog input pin ~ 20 pf + ~ 20 v ? ~ 0.7 v < 2 pf input protection device 400 na junction leakage diffusion and poly coupler 4 k w * this analog switch is closed only during the 12-cycle sample time. *
motorola m68hc11 k series 62 MC68HC11Kts/d ccf ?conversions complete flag 0 = write to adctl is complete 1 = a/d conversion cycle is complete bit 6 ?not implemented always reads zero scan ?ontinuous scan control 0 = do four conversions and stop 1 = convert four channels in selected group continuously mult ?ultiple channel/single channel control 0 = convert single channel selected 1 = convert four channels in selected group cd:ca ?hannel select d through a *used for factory testing adctl ?/d control/status $0030 bit 7 654321 bit 0 ccf scan mult cd cc cb ca reset: 0000000 0 table 9 a/d converter channel assignments channel select control bits channel signal result in adrx if mult = 1 cd cc cb ca 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 an0 an1 an2 an3 adr1 adr2 adr3 adr4 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 an4 an5 an6 an7 adr1 adr2 adr3 adr4 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 reserved reserved reserved reserved 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 v rh * v rl * (v rh )/2* reserved* adr1 adr2 adr3 adr4 adr[4:1] ?/d results $0031 ?$0034 $0031 bit 7 654321 bit 0 adr1 $0032 bit 7 654321 bit 0 adr2 $0033 bit 7 654321 bit 0 adr3 $0034 bit 7 654321 bit 0 adr4
m68hc11 k series motorola MC68HC11Kts/d 63 adpu ?/d converter power-up 0 = a/d converter powered down 1 = a/d converter powered up csel ?clock select 0 = a/d and eeprom use system e clock 1 = a/d and eeprom use internal rc clock source irqe ?rq select edge sensitive only refer to 5 resets and interrupts dly ?nable oscillator startup delay on exit from stop refer to 5 resets and interrupts cme ?lock monitor enable refer to 5 resets and interrupts fcme ?orce clock monitor enable refer to 5 resets and interrupts cr[1:0] ?op timer rate select refer to 10 main timer option ?ystem configuration options $0039 bit 7 654321 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0001000 0
motorola m68hc11 k series 64 MC68HC11Kts/d 10 main timer the timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. a timer overflow function allows software to extend the timing capability of the system beyond the 16- bit range of the counter. the timer has three channels for input capture, four channels for output compare, and one channel that can be configured as a fourth input capture or a fifth output compare. in addition, the timing system in- cludes pulse accumulator and real-time interrupt (rti) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the cop. refer to 11 pulse accumulator and 10.1 real-time interrupt for further information about these func- tions. refer to the following table for a summary of the crystal-related frequencies and periods. table 10 timer summary control bits common system frequencies definition 8.0 mhz 12.0 mhz 16.0 mhz xtal 2.0 mhz 3.0 mhz 4.0 mhz e pr[1:0] main timer count rates (period length) 0 0 1 count overflow 500 ns 32.768 ms 333 ns 21.845 ms 250 ns 16.384 ms 1/e 2 16 /e 0 1 1 count overflow 2.0 m s 131.07 ms 1.333 m s 87.381 ms 1.0 m s 65.536 ms 4/e 2 18 /e 1 0 1 count overflow 4.0 m s 262.14 ms 2.667 m s 174.76 ms 2.0 m s 131.07 ms 8/e 2 19 /e 1 1 1 count overflow 8.0 m s 524.29 ms 5.333 m s 349.52 ms 4.0 m s 262.14 ms 16/e 2 20 /e rtr[1:0] periodic (rti) interrupt rates (period length) 0 0 0 1 1 0 1 1 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms 2.048 ms 4.096 ms 8.192 ms 16.384 ms 2 13 /e 2 14 /e 2 15 /e 2 16 /e cr[1:0] cop watchdog timeout rates (period length) 0 0 0 1 1 0 1 1 16.384 ms 65.536 ms 262.14 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms 8.192 ms 32.768 ms 131.07 ms 524.28 ms 2 15 /e 2 17 /e 2 19 /e 2 21 /e timeout tolerance (? ms/+...) 16.4 ms 10.9 ms 8.192 ms 2 15 /e
m68hc11 k series motorola MC68HC11Kts/d 65 figure 17 timer block diagram pa3 oc5/ ic4/ oc1 16-bit latch clk tic1 (hi) 16-bit comparator = ic3f oc2f oc3f i4/o5f tflg1 tmsk1 ic1f ic1i 3 ic2f ic2i 2 ic3i 1 oc4f i4/o5i 16-bit timer bus 16-bit free-running counter tcnt (hi) tof toi 9 pr1 pr0 prescaler?ivide by 1, 4, 8, or 16 i4/o5 oc1i 8 foc1 oc2i 7 foc2 oc3i 6 foc3 oc4i 5 foc4 4 foc5 status flags force output compare interrupt enables port a oc5 ic4 cforc 16-bit timer bus oc1f bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 pin functions tcnt (lo) pa2/ ic1 tic1 (lo) 16-bit latch clk tic2 (hi) tic2 (lo) 16-bit latch clk tic3 (hi) tic3 (lo) toc1 (hi) toc1 (lo) toc2 (hi) toc2 (lo) toc3 (hi) toc3 (lo) toc4 (hi) toc4 (lo) 16-bit latch clk ti4/o5 (hi) ti4/o5 (lo) 16-bit comparator = 16-bit comparator = 16-bit comparator = 16-bit comparator = mcu eclk interrupt requests (further qualified by i-bit in ccr) pin control pa7/ oc1/ pai pa6/ oc2/ oc1 pa5/ oc3/ oc1 pa4/ oc4/ oc1 pa1/ ic2 pa0/ ic3 to pulse accumulator taps for rti, cop watchdog and pulse accumulator
motorola m68hc11 k series 66 MC68HC11Kts/d foc[5:1] ?orce output compare write ones to force compare(s) 0 = not affected 1 = output x action occurs bits [2:0] ?ot implemented always read zero set bit(s) to enable oc1 to control corresponding pin(s) of port a bits [2:0] ?ot implemented always read zero if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] ?ot implemented always read zero tcnt resets to $0000. in normal modes, tcnt is read only. ticx not affected by reset cforc ?imer compare force $000b bit 7 654321 bit 0 foc1 foc2 foc3 foc4 foc5 reset: 0000000 0 oc1m ?utput compare 1 mask $000c bit 7 654321 bit 0 oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 reset: 0000000 0 oc1d ?utput compare 1 data $000d bit 7 654321 bit 0 oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 reset: 0000000 0 tcnt ?imer count $000e, $000f $000e bit 15 14 13 12 11 10 9 bit 8 high tcnt $000f bit 7 654321 bit 0 low tic1?ic3 ?imer input capture $0010?0015 $0010 bit 15 14 13 12 11 10 9 bit 8 high tic1 $0011 bit 7 654321 bit 0 low $0012 bit 15 14 13 12 11 10 9 bit 8 high tic2 $0013 bit 7 654321 bit 0 low $0014 bit 15 14 13 12 11 10 9 bit 8 high tic3 $0015 bit 7 654321 bit 0 low
m68hc11 k series motorola MC68HC11Kts/d 67 all tocx register pairs reset to ones ($ffff). this is a shared register and is either input capture 4 or output compare 5 depending on the state of bit i4/o5 in pactl. writes to ti4/o5 have no effect when this register is configured as input capture 4. the ti4/o5 register pair resets to ones ($ffff). om[5:2] ?utput mode ol[5:2] ?utput level toc1?oc4 ?imer output compare $0016?001d $0016 bit 15 14 13 12 11 10 9 bit 8 high toc1 $0017 bit 7 654321 bit 0 low $0018 bit 15 14 13 12 11 10 9 bit 8 high toc2 $0019 bit 7 654321 bit 0 low $001a bit 15 14 13 12 11 10 9 bit 8 high toc3 $001b bit 7 654321 bit 0 low $001c bit 15 14 13 12 11 10 9 bit 8 high toc4 $001d bit 7 654321 bit 0 low ti4/o5 ?imer input capture 4/output compare 5 $001e?001f $001e bit 15 14 13 12 11 10 9 bit 8 high $001f bit 7 654321 bit 0 low tctl1 ?imer control 1 $0020 bit 7 654321 bit 0 om2 ol2 om3 ol3 om4 ol4 om5 ol5 reset: 0000000 0 omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one tctl2 ?imer control 2 $0021 bit 7 654321 bit 0 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a reset: 00000000 table 11 timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge
motorola m68hc11 k series 68 MC68HC11Kts/d oc1i?c4i ?utput compare x interrupt enable if the ocxf flag bit is set while the ocxi enable bit is set, a hardware interrupt sequence is requested. i4/o5i ?nput capture 4 or output compare 5 interrupt enable when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt bit. when i4/o5 in pactl is zero, i4/o5i is the output compare 5 interrupt control bit. ic1i?c3i ?nput capture x interrupt enable if the icxf flag bit is set while the icxi enable bit is set, a hardware interrupt sequence is requested. clear flags by writing a one to the corresponding bit position(s). oc1f?c5f ?utput compare x flag set each time the counter matches output compare x value i4/o5f ?nput capture 4/output compare 5 flag set by ic4 or oc5, depending on which function was enabled by i4/o5 of pactl ic1f?c3f ?nput capture x flag set each time a selected active edge is detected on the icx input line note control bits in tmsk1 correspond bit for bit with flag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. toi ?imer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = timer overflow interrupt enabled rtii ?eal-time interrupt enable 0 = rtif interrupts disabled 1 = interrupt requested when rtif is set to one. paovi ?ulse accumulator overflow interrupt enable refer to 11 pulse accumulator . paii ?ulse accumulator interrupt enable refer to 11 pulse accumulator . tmsk1 ?imer interrupt mask 1 $0022 bit 7 654321 bit 0 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i reset: 00000000 tflg1 ?imer interrupt flag 1 $0023 bit 7 654321 bit 0 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f reset: 0000000 0 tmsk2 ?imer interrupt mask 2 $0024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 69 note control bits [7:4] in tmsk2 correspond bit for bit with flag bits [7:4] in tflg2. ones in tmsk2 enable the corresponding interrupt sources. bits [3:2] ?ot implemented always read zero pr[1:0] ?imer prescaler select in normal modes, pr1 and pr0 can only be written once, and the write must occur within 64 cycles after reset. refer to table 10 for specific timing values. clear flags by writing a one to the corresponding bit position(s). tof ?imer overflow flag set when tcnt changes from $ffff to $0000 rtif ?eal-time (periodic) interrupt flag 0 = no rti interrupt 1 = rti interrupt request pending paovf ?ulse accumulator overflow flag refer to 11 pulse accumulator . paif ?ulse accumulator input edge flag refer to 11 pulse accumulator . bits [3:0] ?ot implemented always read zero bit 7 ?ot implemented always read zero paen ?ulse accumulator system enable refer to 11 pulse accumulator . pamod ?ulse accumulator mode refer to 11 pulse accumulator . pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16 tflg2 ?imer interrupt flag 2 $0025 bit 7 654321 bit 0 tof rtif paovf paif reset: 0000000 0 pactl ?ulse accumulator control $0026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 0000000 0
motorola m68hc11 k series 70 MC68HC11Kts/d pedge ?ulse accumulator edge control refer to 11 pulse accumulator . bit 3 ?ot implemented always reads zero i4/o5 ?nput capture 4/output compare 5 configure ti4/o5 for input capture or output compare 0 = oc5 enabled 1 = ic4 enabled rtr[1:0] ?eal-time interrupt (rti) rate refer to 10.1 real-time interrupt . 10.1 real-time interrupt these rates are a function of the mcu oscillator frequency and the value of the software-accessible control bits, rtr1 and rtr0. these bits determine the rate at which interrupts are requested by the rti system. the rti system is driven by an e divided by 2 13 rate clock compensated so that it is inde- pendent of the timer prescaler. the rtr1 and rtr0 control bits select an additional division factor. rti is set to its fastest rate by default out of reset and can be changed at any time. table 12 real-time interrupt rates (period length) period length period length rtr[1:0] selected e = 2.0 mhz e = 3.0 mhz e = 4.0 mhz 0 0 2 13 ? e 4.096 ms 2.731 ms 2.048 ms 0 1 2 14 ? e 8.192 ms 5.461 ms 4.096 ms 1 0 2 15 ? e 16.384 ms 10.923 ms 8.192 ms 1 1 2 16 ? e 32.768 ms 21.845 ms 16.383 ms table 13 real-time interrupt rates (frequency) frequency rtr[1:0] rate selected e = 2.0 mhz e = 3.0 mhz e = 4.0 mhz 0 0 e ? 2 13 244.141 hz 366.211 hz 488.281 hz 0 1 e ?2 14 122.070 hz 183.105 hz 244.141 hz 1 0 e ?2 15 61.035 hz 91.553 hz 122.070 hz 1 1 e ?2 16 30.518 hz 45.776 hz 61.035 hz
m68hc11 k series motorola MC68HC11Kts/d 71 11 pulse accumulator m68hc11 k-series mcus have an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. the counter can be read or written at any time. the port a bit 7 i/o pin can be configured to act as a clock in event counting mode, or as a gate signal to enable a free-running clock (e divided by 64) to the 8-bit counter in gated time accumulation mode. figure 18 pulse accumulator system block diagram common xtal frequencies 8.0 mhz 12.0 mhz 16.0 mhz cpu clock (e) 2.0 mhz 3.0 mhz 4.0 mhz cycle time (1/e) 500 ns 333 ns 250 ns pulse accumulator (gated mode) 1 count (2 6 /e) 32.0 m s 21.33 m s 16.0 m s overflow (2 14 /e) 8.192 ms 5.461 ms 4.096 ms pedge pamod paen pactl control internal data bus pacnt 8-bit counter pa7/ pai/ oc1 interrupt requests paif paovf tflg2 interrupt status paovi paii paovf paovi paif paii tmsk2 int enables 1 2 overflow enable disable flag setting clock pai edge paen paen 2:1 mux output buffer input buffer and edge detector from main timer oc1 data bus pin e ? 64 clock (from main timer) from ddra7
motorola m68hc11 k series 72 MC68HC11Kts/d toi ?imer overflow interrupt enable refer to 10 main timer . rtii ?eal-time interrupt enable refer to 10 main timer . paovi ?ulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = pulse accumulator overflow interrupt enabled paii ?ulse accumulator input interrupt enable 0 = pulse accumulator input interrupt disabled 1 = pulse accumulator input interrupt enabled if paif bit in tflg2 register is set bits [3:2] ?ot implemented always read zero pr[1:0] ?imer prescaler select refer to 10 main timer . note control bits [7:4] in tmsk2 correspond bit for bit with flag bits [7:4] in tflg2. ones in tmsk2 enable the corresponding interrupt sources. clear flags by writing a one to the corresponding bit position(s). tof ?imer overflow enable refer to 10 main timer . rtif ?eal-time interrupt flag refer to 10 main timer . paovf ?ulse accumulator overflow flag set when pacnt changes from $ff to $00 paif ?ulse accumulator input edge flag set each time a selected active edge is detected on the pai input line bits [3:0] ?ot implemented always read zero tmsk2 ?imer interrupt mask 2 $0024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 0000000 0 tflg2 ?imer interrupt flag 2 $0025 bit 7 654321 bit 0 tof rtif paovf paif reset: 0000000 0
m68hc11 k series motorola MC68HC11Kts/d 73 bit 7 ?ot implemented always reads zero paen ?ulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ?ulse accumulator mode 0 = event counter 1 = gated time accumulation pedge ?ulse accumulator edge control 0 = in event mode, falling edges increment counter. in gated accumulation mode, high level enables accumulator and falling edge sets paif. 1 = in event mode, rising edges increment counter. in gated accumulation mode, low level enables accumulator and rising edge sets paif. i4/o5 ?nput capture 4/output compare 5 refer to 10 main timer . rtr[1:0] ?eal-time interrupt rate refer to 10 main timer . can be read and written. pactl ?ulse accumulator control $0026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 0000000 0 pacnt ?ulse accumulator counter $0027 bit 7 654321 bit 0 bit 7 654321 bit 0
motorola m68hc11 k series 74 mc68hc11ts/d 12 pulse-width modulation timer m68hc11 k-series mcus contains a pwm timer that is composed of a four-channel 8-bit modulator. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm provides up to four pulse-width modulated waveforms on port h pins. each channel has its own counter. pairs of counters can be concatenated to create 16-bit pwm outputs based on 16-bit counts. three clock sources (a, b, and s) and a flexible clock select scheme give the pwm system a wide range of frequencies. four control registers configure the pwm outputs ?wclk, pwpol, pwscal, and pwen. the pw- clk register selects the prescale value for the pwm clock sources and enables the 16-bit pwm func- tions. the pwpol register determines each channel's polarity and selects the clock source for each channel. the pwscal register derives a user-scaled clock based on the a clock source, and the pwen register enables the pwm channels. each channel has a separate 8-bit counter, period register, and duty cycle register. the period and duty cycle registers are double buffered so that if they are changed while the channel is enabled, the change does not take effect until the counter rolls over or the channel is disabled. a new period or duty cycle can be forced into effect immediately by writing to the period or duty cycle register and then writing to the counter. with channels configured for 8-bit mode and e = 4 mhz, pwm signals of 40 khz (1% duty cycle reso- lution) to less than 10 hz (approximately 0.4% duty cycle resolution) can be produced. by configuring the channels for 16-bit mode with e = 4 mhz, pwm periods greater than one minute are possible. in 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a pwm frequen- cy of about 60 hz). in the same system, a pwm frequency of 1 khz corresponds to a duty cycle reso- lution of 0.025%.
m68hc11 k series motorola mc68hc11ts/d 75 figure 19 pulse-width modulation block diagram pwdty pwper pwm output ? 128 ? 1 ? 2 ? 4 ? 8 mcu e clock select pckb1 pckb2 pckb3 8-bit counter 8-bit compare = pwscal reset ? 2 clock a clock s pclk1 pclk2 pwen1 pwen2 con12 clock select bit 1 pwdty1 pwcnt1 pwcnt2 8-bit compare = pwdty2 pwper2 pwper1 16-bit pwm control con12 s r q carry reset bit 0 s r q mux ppol1 ppol2 ? 32 ? 64 cnt1 cnt2 q q mux ? 16 ph0/ pw1 8-bit compare = 8-bit compare = 8-bit compare = ph1/ pw2 port h pin control reset 8 8 8 bit 3 pwdty3 pwcnt3 pwcnt4 8-bit compare = pwdty4 pwper4 pwper3 16-bit pwm control con34 s r q carry reset bit 2 s r q mux ppol3 ppol4 q q mux ph2/ pw3 8-bit compare = 8-bit compare = 8-bit compare = ph3/ pw4 reset 8 8 pclk3 pclk4 pwen3 pwen4 con34 clock select cnt3 cnt4 select clock b pcka1 pcka2
motorola m68hc11 k series 76 mc68hc11ts/d con34 ?oncatenate channels 3 and 4 channel 3 is high-order byte, and channel 4 is the low-order byte. the resulting output is available on port h, pin 3. clock source is determined by pclk4. 0 = channels 3 and 4 are separate 8-bit pwms. 1 = channels 3 and 4 are concatenated to create one 16-bit pwm channel. con12 ?oncatenate channels one and two channel 1 is high-order byte, and channel 2 is the low-order byte. the resulting output is available on port h, pin 1. clock source is determined by pclk2. 0 = channels 1 and 2 are separate 8-bit pwms. 1 = channels 1 and 2 are concatenated to create one 16-bit pwm channel. pcka[2:1] ?rescaler for clock a (see also pwscal register) determines the rate of clock a bit 3 ?ot implemented always reads zero pckb[3:1] ?rescaler for clock b determines the rate for clock b pclk4 ?ulse-width channel 4 clock select 0 = clock b is source 1 = clock s is source pwclk ?ulse-width modulation clock select $0060 bit 7 654321 bit 0 con34 con12 pcka2 pcka1 pckb3 pckb2 pckb1 reset: 0000000 0 pcka[2:1] value of clock a 0 0 e 0 1 e/2 1 0 e/4 1 1 e/8 pckb[3:1] value of clock b 0 0 0 e 0 0 1 e/2 0 1 0 e/4 0 1 1 e/8 1 0 0 e/16 1 0 1 e/32 1 1 0 e/64 1 1 1 e/128 pwpol ?ulse-width modulation timer polarity $0061 bit 7 654321 bit 0 pclk4 pclk3 pclk2 pclk1 ppol4 ppol3 ppol2 ppol1 reset: 0000000 0
m68hc11 k series motorola mc68hc11ts/d 77 pclk3 ?ulse-width channel 3 clock select 0 = clock b is source 1 = clock s is source pclk2 ?ulse-width channel 2 clock select 0 = clock a is source 1 = clock s is source pclk1 ?ulse-width channel 1 clock select 0 = clock a is source 1 = clock s is source ppol[4:1] ?ulse-width channel x polarity 0 = pwm channel x output is low at the beginning of the clock cycle and goes high when duty count is reached 1 = pwm channel x output is high at the beginning of the clock cycle and goes low when duty count is reached scaled clock s is generated by dividing clock a by the value in pwscal, then dividing the result by 2. if pwscal = $00, divide clock a by 256, then divide the result by 2. tpwsl ?wm scaled clock test bit (test) factory test only discp ?isable compare scaled e clock (test) factory test only bits [5:4] ?ot implemented always read zero pwen[4:1] ?ulse-width channel 4? 0 = channel disabled 1 = channel enabled pwcnt1?wcnt4 begins count using whichever clock was selected pwscal ?ulse-width modulation timer prescaler $0062 bit 7 654321 bit 0 7654321 0 reset: 0000000 0 pwen ?ulse-width modulation timer enable $0063 bit 7 654321 bit 0 tpwsl discp pwen4 pwen3 pwen2 pwen1 reset: 0000000 0 pwcnt1?wcnt4 ?ulse-width modulation timer counter 1 to 4 $0064?0067 $0064 bit 7 654321 bit 0 pwcnt1 $0065 bit 7 654321 bit 0 pwcnt2 $0066 bit 7 654321 bit 0 pwcnt3 $0067 bit 7 654321 bit 0 pwcnt4 reset: 00000000
motorola m68hc11 k series 78 mc68hc11ts/d pwper1?wper4 determines period of associated pwm channel pwdty1? determines duty cycle of associated pwm channel 12.1 pwm boundary cases certain values written to pwm control registers, counters, etc. can cause outputs that are not what the user might expect. these are referred to as boundary cases. boundary cases occur when the user specifies a value that is either a maximum or a minimum. this value combined with other conditions causes unexpected behavior of the pwm system. the following conditions always cause the corresponding output to be high: pwdtyx = $00, pwperx > $00, and ppolx = 0 pwdtyx 3 pwperx, and ppolx = 1 pwperx = $00 and ppolx = 1 the following conditions always cause the corresponding output to be low: pwdtyx = $00, pwperx > $00, and ppolx = 1 pwdtyx 3 pwperx, and ppolx = 0 pwperx = $00 and ppolx = 0 pwper1?wper4 ?ulse-width modulation timer period 1 to 4 $0068?006b $0068 bit 7 654321 bit 0 pwper1 $0069 bit 7 654321 bit 0 pwper2 $006a bit 7 654321 bit 0 pwper3 $006b bit 7 654321 bit 0 pwper4 reset: 11111111 pwdty1? ?ulse-width modulation timer duty cycle 1 to 4 $006c?006f bit 7 654321 bit 0 $006c bit 7 654321 bit 0 pwdty1 $006d bit 7 654321 bit 0 pwdty2 $006e bit 7 654321 bit 0 pwdty3 $006f bit 7 654321 bit 0 pwdty4 reset: 11111111
m68hc11 k series motorola MC68HC11Kts/d 79
MC68HC11Kts/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver colorado 80217. 1-800-441-2447, (303) 675-2140 mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 81-3-3521-8315 asia pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 mfax is a trademark of motorola, inc. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. mcuinit, mcuasm, mcudebug, and rtek are trademarks of motorola, inc. motorola and the motorola logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.

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